[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Align trap_entry to 4 bytes, as required

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/23173


Change subject: arch/riscv: Align trap_entry to 4 bytes, as required
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arch/riscv: Align trap_entry to 4 bytes, as required

The RISC-V Privileged Architecture spec 1.10 requires that the address part of
mtvec is four-byte aligned. The lower two bits encode a "mode" flag and should
be zero for now.

Add the necessary alignment directive before trap_entry.

Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/arch/riscv/trap_util.S
1 file changed, 1 insertion(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/23173/1

diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index 72a9ae1..8aba48b 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -109,6 +109,7 @@
   .text
 
     .global  trap_entry
+    .align 2	# four byte alignment, as required by mtvec
 trap_entry:
   csrw mscratch, sp
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I83ea23e2c8f984775985ae7d61f80ad75286baaa
Gerrit-Change-Number: 23173
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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