[coreboot-gerrit] Change in coreboot[master]: [TEST, NOTFORMERGE]model_1067x: Use sandybridge CAR

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23169


Change subject: [TEST, NOTFORMERGE]model_1067x: Use sandybridge CAR
......................................................................

[TEST, NOTFORMERGE]model_1067x: Use sandybridge CAR

Change-Id: I99163c48594e2d7236fef0d276700f5fba480905
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/model_1067x/Kconfig
M src/cpu/intel/model_206ax/cache_as_ram.inc
M src/cpu/intel/socket_BGA956/Makefile.inc
3 files changed, 32 insertions(+), 18 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/23169/1

diff --git a/src/cpu/intel/model_1067x/Kconfig b/src/cpu/intel/model_1067x/Kconfig
index 3ea8125..2a961a6 100644
--- a/src/cpu/intel/model_1067x/Kconfig
+++ b/src/cpu/intel/model_1067x/Kconfig
@@ -10,3 +10,11 @@
 	select TSC_SYNC_MFENCE
 	select SUPPORT_CPU_UCODE_IN_CBFS
 	select CPU_INTEL_COMMON
+
+config CACHE_MRC_SIZE_KB
+	int
+	default 512
+
+config DCACHE_RAM_MRC_VAR_SIZE
+	hex
+	default 0x0
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc
index d1678bf..0c6e330 100644
--- a/src/cpu/intel/model_206ax/cache_as_ram.inc
+++ b/src/cpu/intel/model_206ax/cache_as_ram.inc
@@ -94,6 +94,12 @@
 	orl	$MTRR_DEF_TYPE_EN, %eax
 	wrmsr
 
+	/* Enable L2 cache. */
+	movl	$0x11e, %ecx
+	rdmsr
+	orl	$(1 << 8), %eax
+	wrmsr
+
 	/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
 	movl	%cr0, %eax
 	andl	$(~(CR0_CacheDisable | CR0_NoWriteThrough)), %eax
@@ -101,11 +107,11 @@
 	movl	%eax, %cr0
 
 	/* enable the 'no eviction' mode */
-	movl    $NoEvictMod_MSR, %ecx
-	rdmsr
-	orl     $1, %eax
-	andl    $~2, %eax
-	wrmsr
+//	movl    $NoEvictMod_MSR, %ecx
+//	rdmsr
+//	orl     $1, %eax
+//	andl    $~2, %eax
+//	wrmsr
 
 	/* Clear the cache memory region. This will also fill up the cache. */
 	movl	$CACHE_AS_RAM_BASE, %esi
@@ -116,10 +122,10 @@
 	rep	stosl
 
 	/* enable the 'no eviction run' state */
-	movl    $NoEvictMod_MSR, %ecx
-	rdmsr
-	orl     $3, %eax
-	wrmsr
+//	movl    $NoEvictMod_MSR, %ecx
+//	rdmsr
+//	orl     $3, %eax
+//	wrmsr
 
 	post_code(0x26)
 	/* Enable Cache-as-RAM mode by disabling cache. */
@@ -197,17 +203,17 @@
 	post_code(0x32)
 
 	/* Disable the no eviction run state */
-	movl    $NoEvictMod_MSR, %ecx
-	rdmsr
-	andl    $~2, %eax
-	wrmsr
+//	movl    $NoEvictMod_MSR, %ecx
+//	rdmsr
+//	andl    $~2, %eax
+//	wrmsr
 
 	invd
 
 	/* Disable the no eviction mode */
-	rdmsr
-	andl    $~1, %eax
-	wrmsr
+//	rdmsr
+//	andl    $~1, %eax
+//	wrmsr
 
 	post_code(0x33)
 
@@ -311,5 +317,5 @@
 	.word 0x204, 0x205, 0x206, 0x207
 	.word 0x208, 0x209, 0x20A, 0x20B
 	.word 0x20C, 0x20D, 0x20E, 0x20F
-	.word 0x210, 0x211, 0x212, 0x213
+//	.word 0x210, 0x211, 0x212, 0x213
 mtrr_table_end:
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc
index 22c1a7c..674e10d 100644
--- a/src/cpu/intel/socket_BGA956/Makefile.inc
+++ b/src/cpu/intel/socket_BGA956/Makefile.inc
@@ -9,5 +9,5 @@
 subdirs-y += ../speedstep
 
 # Use Intel Core (not Core 2) code for CAR init, any CPU might be used.
-cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc
+cpu_incs-y += $(src)/cpu/intel/model_206ax/cache_as_ram.inc
 romstage-y += ../car/romstage.c

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I99163c48594e2d7236fef0d276700f5fba480905
Gerrit-Change-Number: 23169
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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