[coreboot-gerrit] Change in coreboot[master]: soc/intel/{apollolake, cannonlake, skylake}: Add option to select FSP...
Subrata Banik (Code Review)
gerrit at coreboot.org
Mon Jan 8 11:48:54 CET 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23161
Change subject: soc/intel/{apollolake, cannonlake, skylake}: Add option to select FSP_CAR
......................................................................
soc/intel/{apollolake, cannonlake, skylake}: Add option to select FSP_CAR
This patch provides an option for non-chrome devices to make use of
FSP-T for performing cache-as-ram initialization. Majority of IOTG users
are using FSP-T for CAR implementation and couldn't able to select FSP_CAR
kconfig from SoC without conflicting with existing CAR config.
TEST=Ensures for Chrome platform CAR_NEM_ENHANCED config is getting
selected and for other non Chrome OS platform respective FSP_CAR
config is enabled.
Change-Id: If565b649fe1c2abdbcf0a740c15db7253c084ae7
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/apollolake/Kconfig
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/skylake/Kconfig
3 files changed, 32 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/23161/1
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 2d5363d..87d59aa 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -286,8 +286,9 @@
choice
prompt "Cache-as-ram implementation"
- default CAR_CQOS if !SOC_INTEL_GLK
- default CAR_NEM
+ default CAR_CQOS if !SOC_INTEL_GLK && MAINBOARD_HAS_CHROMEOS
+ default CAR_NEM if MAINBOARD_HAS_CHROMEOS
+ default USE_APOLLOLAKE_FSP_CAR
help
This option allows you to select how cache-as-ram (CAR) is set up.
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 715cdf4..6770be9 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -24,7 +24,6 @@
select HAVE_INTEL_FIRMWARE
select HAVE_MONOTONIC_TIMER
select HAVE_SMI_HANDLER
- select INTEL_CAR_NEM_ENHANCED
select INTEL_GMA_ACPI
select INTEL_GMA_ADD_VBT_DATA_FILE if RUN_FSP_GOP
select IOAPIC
@@ -43,7 +42,6 @@
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_BLOCK
select SOC_INTEL_COMMON_BLOCK_ACPI
- select SOC_INTEL_COMMON_BLOCK_CAR
select SOC_INTEL_COMMON_BLOCK_CPU
select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT
select SOC_INTEL_COMMON_BLOCK_CSE
@@ -175,4 +173,31 @@
hex
default 0x2000
+choice
+ prompt "Cache-as-ram implementation"
+ default CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS
+ default USE_CANNONLAKE_FSP_CAR
+ help
+ This option allows you to select how cache-as-ram (CAR) is set up.
+
+config CAR_NEM_ENHANCED
+ bool "Enhanced Non-evict mode"
+ select SOC_INTEL_COMMON_BLOCK_CAR
+ select INTEL_CAR_NEM_ENHANCED
+ help
+ A current limitation of NEM (Non-Evict mode) is that code and data sizes
+ are derived from the requirement to not write out any modified cache line.
+ With NEM, if there is no physical memory behind the cached area,
+ the modified data will be lost and NEM results will be inconsistent.
+ ENHANCED NEM guarantees that modified data is always
+ kept in cache while clean data is replaced.
+
+config USE_CANNONLAKE_FSP_CAR
+ bool "Use FSP CAR"
+ select FSP_CAR
+ help
+ Use FSP APIs to initialize & tear Down the Cache-As-Ram.
+
+endchoice
+
endif
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 7bb16d2..e82914d 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -285,7 +285,8 @@
choice
prompt "Cache-as-ram implementation"
- default CAR_NEM_ENHANCED
+ default CAR_NEM_ENHANCED if MAINBOARD_HAS_CHROMEOS
+ default USE_SKYLAKE_FSP_CAR
help
This option allows you to select how cache-as-ram (CAR) is set up.
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: If565b649fe1c2abdbcf0a740c15db7253c084ae7
Gerrit-Change-Number: 23161
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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