[coreboot-gerrit] Change in coreboot[master]: [UNTESTED]sb/intel/common/spi.c: Add a SPI write protect function

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/23146


Change subject: [UNTESTED]sb/intel/common/spi.c: Add a SPI write protect function
......................................................................

[UNTESTED]sb/intel/common/spi.c: Add a SPI write protect function

Could be useful to WP for instance the MRC_CACHE region.

Change-Id: Id0a9a0de639c5d6761a77a56ceba6d89110a4ea1
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/southbridge/intel/common/spi.c
1 file changed, 69 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/23146/1

diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c
index 63f6e57..a0c58a6 100644
--- a/src/southbridge/intel/common/spi.c
+++ b/src/southbridge/intel/common/spi.c
@@ -83,6 +83,7 @@
 	uint16_t preop;
 	uint16_t optype;
 	uint8_t opmenu[8];
+	uint32_t pbr[3];
 } __packed ich7_spi_regs;
 
 typedef struct ich9_spi_regs {
@@ -134,6 +135,7 @@
 	uint8_t *status;
 	uint16_t *control;
 	uint32_t *bbar;
+	uint32_t *fpr;
 } ich_spi_controller;
 
 static ich_spi_controller cntlr;
@@ -319,6 +321,7 @@
 		cntlr.control = &ich7_spi->spic;
 		cntlr.bbar = &ich7_spi->bbar;
 		cntlr.preop = &ich7_spi->preop;
+		cntlr.fpr = ich7_spi->pbr;
 	} else {
 		ich9_spi = (ich9_spi_regs *)(rcrb + 0x3800);
 		cntlr.ich9_spi = ich9_spi;
@@ -335,6 +338,7 @@
 		cntlr.control = (uint16_t *)ich9_spi->ssfc;
 		cntlr.bbar = &ich9_spi->bbar;
 		cntlr.preop = &ich9_spi->preop;
+		cntlr.fpr = ich9_spi->pr;
 
 		if (cntlr.hsfs & HSFS_FDV) {
 			writel_ (4, &ich9_spi->fdoc);
@@ -953,11 +957,76 @@
 	return 0;
 }
 
+#define SPI_FPR_SHIFT		12
+#define ICH7_SPI_FPR_MASK		0xfff
+#define ICH9_SPI_FPR_MASK		0x1fff
+#define SPI_FPR_BASE_SHIFT	0
+#define ICH7_SPI_FPR_LIMIT_SHIFT	12
+#define ICH9_SPI_FPR_LIMIT_SHIFT	16
+#define ICH9_SPI_FPR_RPE		(1 << 15) /* Read Protect */
+#define SPI_FPR_WPE		(1 << 31) /* Write Protect */
+#define ICH7_SPI_FPR(base, limit)	\
+	(((((limit) >> SPI_FPR_SHIFT) & ICH7_SPI_FPR_MASK) << ICH7_SPI_FPR_LIMIT_SHIFT) |\
+	 ((((base) >> SPI_FPR_SHIFT) & ICH7_SPI_FPR_MASK) << SPI_FPR_BASE_SHIFT))
+#define ICH9_SPI_FPR(base, limit)	\
+	(((((limit) >> SPI_FPR_SHIFT) & ICH9_SPI_FPR_MASK) << ICH9_SPI_FPR_LIMIT_SHIFT) |\
+	 ((((base) >> SPI_FPR_SHIFT) & ICH9_SPI_FPR_MASK) << SPI_FPR_BASE_SHIFT))
+
+/*
+ * Protect range of SPI flash defined by [start, start+size-1] using Flash
+ * Protected Range (FPR) register if available.
+ */
+static int spi_flash_protect(const struct spi_flash *flash,
+			const struct region *region)
+{
+	u32 start = region_offset(region);
+	u32 end = start + region_sz(region) - 1;
+	u32 reg;
+	int fpr;
+	uintptr_t fpr_base;
+	const int spibar_fpr_max = (sizeof(cntlr.fpr) / sizeof(cntlr.fpr[0]));
+
+	fpr_base = (uintptr_t)cntlr.fpr;
+
+	/* Find first empty FPR */
+	for (fpr = 0; fpr < spibar_fpr_max; fpr++) {
+		reg = read32((void *)fpr_base);
+		if (reg == 0)
+			break;
+		fpr_base += sizeof(uint32_t);
+	}
+
+	if (fpr >= spibar_fpr_max) {
+		printk(BIOS_ERR, "ERROR: No SPI FPR free!\n");
+		return -1;
+	}
+
+	/* Set protected range base and limit */
+	if (IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_I82801GX))
+		reg = ICH7_SPI_FPR(start, end) | SPI_FPR_WPE;
+	else
+		reg = ICH9_SPI_FPR(start, end) | SPI_FPR_WPE;		
+
+	/* Set the FPR register and verify it is protected */
+	write32((void *)fpr_base, reg);
+	reg = read32((void *)fpr_base);
+	if (!(reg & SPI_FPR_WPE)) {
+		printk(BIOS_ERR, "ERROR: Unable to set SPI FPR %d\n", fpr);
+		return -1;
+	}
+
+	printk(BIOS_INFO, "%s: FPR %d is enabled for range 0x%08x-0x%08x\n",
+	       __func__, fpr, start, end);
+	return 0;
+}
+
+
 static const struct spi_ctrlr spi_ctrlr = {
 	.xfer = spi_ctrlr_xfer,
 	.xfer_vector = spi_xfer_two_vectors,
 	.max_xfer_size = member_size(ich9_spi_regs, fdata),
 	.flash_probe = spi_flash_programmer_probe,
+	.flash_protect = spi_flash_protect,
 };
 
 const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id0a9a0de639c5d6761a77a56ceba6d89110a4ea1
Gerrit-Change-Number: 23146
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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