[coreboot-gerrit] Change in coreboot[master]: src/soc/intel/apollolake: Add gpio groups

[Bora Guvendik (Code Review)]

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/23126


Change subject: src/soc/intel/apollolake: Add gpio groups
......................................................................

src/soc/intel/apollolake: Add gpio groups

Add the information about groups within each community.

Change-Id: Ib730d2c69f0f611dfbc0949f51eaba8ba1d0fba4
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/soc/intel/apollolake/gpio_apl.c
1 file changed, 36 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/23126/1

diff --git a/src/soc/intel/apollolake/gpio_apl.c b/src/soc/intel/apollolake/gpio_apl.c
index a774470..c01e153 100644
--- a/src/soc/intel/apollolake/gpio_apl.c
+++ b/src/soc/intel/apollolake/gpio_apl.c
@@ -21,12 +21,40 @@
 #include <soc/pcr_ids.h>
 #include <soc/pm.h>
 
+#define APL_GPP(s, e)				\
+	{						\
+		.first_pad = (s),			\
+		.size = ((e) - (s) + 1),		\
+	}
+
 static const struct reset_mapping rst_map[] = {
 	{ .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
 	{ .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
 	{ .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
 };
 
+static const struct pad_group apl_community_n_groups[] = {
+	APL_GPP(N_OFFSET, GPIO_31),	/* NORTH 0 */
+	APL_GPP(GPIO_32, TRST_B),	/* NORTH 1 */
+	APL_GPP(TMS, SVID0_CLK),	/* NORTH 2 */
+};
+
+static const struct pad_group apl_community_w_groups[] = {
+	APL_GPP(W_OFFSET, OSC_CLK_OUT_1),/* WEST 0 */
+	APL_GPP(OSC_CLK_OUT_2, SUSPWRDNACK),/* WEST 1 */
+};
+
+static const struct pad_group apl_community_sw_groups[] = {
+	APL_GPP(SW_OFFSET, SMB_ALERTB),	/* SOUTHWEST 0 */
+	APL_GPP(SMB_CLK, LPC_FRAMEB),	/* SOUTHWEST 1 */
+};
+
+static const struct pad_group apl_community_nw_groups[] = {
+	APL_GPP(NW_OFFSET, PROCHOT_B),	/* NORTHWEST 0 */
+	APL_GPP(PMIC_I2C_SCL, GPIO_106),/* NORTHWEST 1 */
+	APL_GPP(GPIO_109, GPIO_123),	/* NORTHWEST 2 */
+};
+
 static const struct pad_community apl_gpio_communities[] = {
 	{
 		.port = PID_GPIO_SW,
@@ -43,6 +71,8 @@
 		.acpi_path = "\\_SB.GPO3",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = apl_community_sw_groups,
+		.num_groups = ARRAY_SIZE(apl_community_sw_groups),
 	}, {
 		.port = PID_GPIO_W,
 		.first_pad = W_OFFSET,
@@ -58,6 +88,8 @@
 		.acpi_path = "\\_SB.GPO2",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = apl_community_w_groups,
+		.num_groups = ARRAY_SIZE(apl_community_w_groups),
 	}, {
 		.port = PID_GPIO_NW,
 		.first_pad = NW_OFFSET,
@@ -73,6 +105,8 @@
 		.acpi_path = "\\_SB.GPO1",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = apl_community_nw_groups,
+		.num_groups = ARRAY_SIZE(apl_community_nw_groups),
 	}, {
 		.port = PID_GPIO_N,
 		.first_pad = N_OFFSET,
@@ -89,6 +123,8 @@
 		.acpi_path = "\\_SB.GPO0",
 		.reset_map = rst_map,
 		.num_reset_vals = ARRAY_SIZE(rst_map),
+		.groups = apl_community_n_groups,
+		.num_groups = ARRAY_SIZE(apl_community_n_groups),
 	}
 };
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ib730d2c69f0f611dfbc0949f51eaba8ba1d0fba4
Gerrit-Change-Number: 23126
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
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