[coreboot-gerrit] Change in coreboot[master]: Initial support for new mainboard Cheza
T.Michael Turney (Code Review)
gerrit at coreboot.org
Mon Feb 26 23:43:33 CET 2018
Hello mturney mturney,
I'd like you to do a code review. Please visit
https://review.coreboot.org/23876
to review the following change.
Change subject: Initial support for new mainboard Cheza
......................................................................
Initial support for new mainboard Cheza
Successful build with minimal configuration
Most functions are stubbed out, w/minimal content
Change-Id: I91226c2bc88dd10bc2590d1689267306763bb63e
Signed-off-by: T.Michael Turney <mturney at codeaurora.org>
---
A src/mainboard/google/cheza/Kconfig
A src/mainboard/google/cheza/Kconfig.name
A src/mainboard/google/cheza/Makefile.inc
A src/mainboard/google/cheza/board_info.txt
A src/mainboard/google/cheza/bootblock.c
A src/mainboard/google/cheza/chromeos.c
A src/mainboard/google/cheza/chromeos.fmd
A src/mainboard/google/cheza/devicetree.cb
A src/mainboard/google/cheza/mainboard.c
A src/mainboard/google/cheza/memlayout.ld
A src/mainboard/google/cheza/romstage.c
A src/soc/qualcomm/sdm845/Kconfig
A src/soc/qualcomm/sdm845/Makefile.inc
A src/soc/qualcomm/sdm845/bootblock.c
A src/soc/qualcomm/sdm845/cbmem.c
A src/soc/qualcomm/sdm845/i2c.c
A src/soc/qualcomm/sdm845/include/soc/gpio.h
A src/soc/qualcomm/sdm845/include/soc/memlayout.ld
A src/soc/qualcomm/sdm845/soc.c
A src/soc/qualcomm/sdm845/spi.c
A src/soc/qualcomm/sdm845/stage_entry.c
A src/soc/qualcomm/sdm845/timer.c
22 files changed, 708 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/23876/1
diff --git a/src/mainboard/google/cheza/Kconfig b/src/mainboard/google/cheza/Kconfig
new file mode 100644
index 0000000..4f3e94e
--- /dev/null
+++ b/src/mainboard/google/cheza/Kconfig
@@ -0,0 +1,57 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config BOARD_GOOGLE_CHEZA_COMMON # Umbrella option to be selected by variant boards.
+ def_bool n
+
+if BOARD_GOOGLE_CHEZA_COMMON
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_2048
+ select COMMON_CBFS_SPI_WRAPPER
+ select SOC_QUALCOMM_SDM845
+ select SPI_FLASH
+ select MAINBOARD_HAS_CHROMEOS
+
+config VBOOT
+ select VBOOT_VBNV_FLASH
+ select TPM
+
+config MAINBOARD_DIR
+ string
+ default google/cheza
+
+config MAINBOARD_VENDOR
+ string
+ default "Google"
+
+##########################################################
+#### Update below when adding a new derivative board. ####
+##########################################################
+config DEVICETREE
+ string
+ default "devicetree.cb"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Cheza" if BOARD_GOOGLE_CHEZA
+
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "CHEZA TEST 845" if BOARD_GOOGLE_CHEZA
+
+endif # BOARD_GOOGLE_CHEZA_COMMON
diff --git a/src/mainboard/google/cheza/Kconfig.name b/src/mainboard/google/cheza/Kconfig.name
new file mode 100644
index 0000000..2697c0b
--- /dev/null
+++ b/src/mainboard/google/cheza/Kconfig.name
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config BOARD_GOOGLE_CHEZA
+ bool "Cheza (Qualcomm Chromebook)"
+ select BOARD_GOOGLE_CHEZA_COMMON
diff --git a/src/mainboard/google/cheza/Makefile.inc b/src/mainboard/google/cheza/Makefile.inc
new file mode 100644
index 0000000..de33112
--- /dev/null
+++ b/src/mainboard/google/cheza/Makefile.inc
@@ -0,0 +1,29 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += memlayout.ld
+bootblock-y += chromeos.c
+bootblock-y += bootblock.c
+
+verstage-y += memlayout.ld
+verstage-y += chromeos.c
+
+romstage-y += memlayout.ld
+romstage-y += chromeos.c
+romstage-y += romstage.c
+
+ramstage-y += memlayout.ld
+ramstage-y += chromeos.c
+ramstage-y += mainboard.c
diff --git a/src/mainboard/google/cheza/board_info.txt b/src/mainboard/google/cheza/board_info.txt
new file mode 100644
index 0000000..5498070
--- /dev/null
+++ b/src/mainboard/google/cheza/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Cheza Qualcomm reference board
+Category: eval
+ROM protocol: QSPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/cheza/bootblock.c b/src/mainboard/google/cheza/bootblock.c
new file mode 100644
index 0000000..aceb61b
--- /dev/null
+++ b/src/mainboard/google/cheza/bootblock.c
@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+
+void bootblock_mainboard_early_init(void)
+{
+
+}
+
+void bootblock_mainboard_init(void)
+{
+
+}
diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c
new file mode 100644
index 0000000..98c1285
--- /dev/null
+++ b/src/mainboard/google/cheza/chromeos.c
@@ -0,0 +1,34 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <boot/coreboot_tables.h>
+
+int get_write_protect_state(void);
+int get_recovery_mode_switch(void);
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+
+}
+
+int get_write_protect_state(void)
+{
+ return 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+ return 0;
+}
diff --git a/src/mainboard/google/cheza/chromeos.fmd b/src/mainboard/google/cheza/chromeos.fmd
new file mode 100644
index 0000000..d00b5c0
--- /dev/null
+++ b/src/mainboard/google/cheza/chromeos.fmd
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+FLASH at 0x0 0x200000 {
+ WP_RO at 0x0 0x000AB100 {
+ RO_SECTION at 0x0 0x000A9100 {
+ BOOTBLOCK at 0 128K
+ COREBOOT(CBFS)@0x20000 0x80000
+ FMAP at 0xA0000 0x1000
+ GBB at 0xA1000 0x8000
+ RO_FRID at 0xA9000 0x100
+ }
+ RO_VPD at 0xA9100 0x2000
+ }
+ RW_NVRAM at 0xAB100 0x2000
+ RW_ELOG at 0xAD100 0x2000
+ RW_VPD at 0xAF100 0x2000
+ RW_CDT at 0xB1100 0x2000
+
+ RW_SECTION_A at 0xB3100 0x8A100 {
+ VBLOCK_A at 0x0 0x2000
+ FW_MAIN_A(CBFS)@0x2000 0x80000
+ RW_FWID_A at 0x82000 0x100
+ RW_DDR_TRAINING_A at 0x82100 0x4000
+ RW_XBL_BUFFER_A at 0x86100 0x4000
+ }
+ RW_SHARED at 0x13D200 0x1000 {
+ SHARED_DATA at 0x0 0x1000
+ }
+ RW_SECTION_B at 0x13E200 0x8A100 {
+ VBLOCK_B at 0x0 0x2000
+ FW_MAIN_B(CBFS)@0x2000 0x80000
+ RW_FWID_B at 0x82000 0x100
+ RW_DDR_TRAINING_B at 0x82100 0x4000
+ RW_XBL_BUFFER_B at 0x86100 0x4000
+ }
+}
diff --git a/src/mainboard/google/cheza/devicetree.cb b/src/mainboard/google/cheza/devicetree.cb
new file mode 100644
index 0000000..41942f1
--- /dev/null
+++ b/src/mainboard/google/cheza/devicetree.cb
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/qualcomm/sdm845
+ device cpu_cluster 0 on end
+end
diff --git a/src/mainboard/google/cheza/mainboard.c b/src/mainboard/google/cheza/mainboard.c
new file mode 100644
index 0000000..6a3fad9
--- /dev/null
+++ b/src/mainboard/google/cheza/mainboard.c
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+#include <bootblock_common.h>
+
+static void mainboard_init(device_t dev)
+{
+
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .name = CONFIG_MAINBOARD_PART_NUMBER,
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/cheza/memlayout.ld b/src/mainboard/google/cheza/memlayout.ld
new file mode 100644
index 0000000..1ae10a5
--- /dev/null
+++ b/src/mainboard/google/cheza/memlayout.ld
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+ #include <soc/memlayout.ld>
diff --git a/src/mainboard/google/cheza/romstage.c b/src/mainboard/google/cheza/romstage.c
new file mode 100644
index 0000000..8f25898
--- /dev/null
+++ b/src/mainboard/google/cheza/romstage.c
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/exception.h>
+#include <cbmem.h>
+#include <program_loading.h>
+
+void main(void)
+{
+ exception_init();
+ cbmem_initialize_empty();
+ run_ramstage();
+}
diff --git a/src/soc/qualcomm/sdm845/Kconfig b/src/soc/qualcomm/sdm845/Kconfig
new file mode 100644
index 0000000..747052e
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/Kconfig
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SOC_QUALCOMM_SDM845
+ bool
+ default n
+ select ARCH_BOOTBLOCK_ARMV8_64
+ select ARCH_RAMSTAGE_ARMV8_64
+ select ARCH_ROMSTAGE_ARMV8_64
+ select ARCH_VERSTAGE_ARMV8_64
+ select BOOTBLOCK_CONSOLE
+ select GENERIC_GPIO_LIB
+ select GENERIC_UDELAY
+ select HAVE_MONOTONIC_TIMER
+
+if SOC_QUALCOMM_SDM845
+
+config VBOOT
+ select VBOOT_SEPARATE_VERSTAGE
+ select VBOOT_RETURN_FROM_VERSTAGE
+ select VBOOT_OPROM_MATTERS
+ select VBOOT_STARTS_IN_BOOTBLOCK
+
+endif
diff --git a/src/soc/qualcomm/sdm845/Makefile.inc b/src/soc/qualcomm/sdm845/Makefile.inc
new file mode 100644
index 0000000..1d76649
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/Makefile.inc
@@ -0,0 +1,54 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2018, The Linux Foundation. All rights reserved.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+ifeq ($(CONFIG_SOC_QUALCOMM_SDM845),y)
+
+################################################################################
+bootblock-y += bootblock.c
+bootblock-y += timer.c
+bootblock-y += spi.c
+bootblock-y += i2c.c
+
+################################################################################
+verstage-y += stage_entry.c
+verstage-y += timer.c
+verstage-y += spi.c
+verstage-y += i2c.c
+
+################################################################################
+romstage-y += stage_entry.c
+romstage-y += timer.c
+romstage-y += spi.c
+romstage-y += cbmem.c
+romstage-y += i2c.c
+
+################################################################################
+ramstage-y += stage_entry.c
+ramstage-y += soc.c
+ramstage-y += timer.c
+ramstage-y += spi.c
+ramstage-y += cbmem.c
+ramstage-y += i2c.c
+
+################################################################################
+
+CPPFLAGS_common += -Isrc/soc/qualcomm/sdm845/include
+
+$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
+ @printf "Generating: $(subst $(obj)/,,$(@))\n"
+ @mkdir -p $(dir $@)
+ cp $(objcbfs)/bootblock.raw.bin $(objcbfs)/bootblock.bin
+
+endif
diff --git a/src/soc/qualcomm/sdm845/bootblock.c b/src/soc/qualcomm/sdm845/bootblock.c
new file mode 100644
index 0000000..3440dd7
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/bootblock.c
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <bootblock_common.h>
+#include <string.h>
+
+extern u8 _bss[], _ebss[];
+
+void bootblock_soc_early_init(void)
+{
+ memset(_bss, 0, (_ebss-_bss));
+}
+
+void bootblock_soc_init(void)
+{
+
+}
diff --git a/src/soc/qualcomm/sdm845/cbmem.c b/src/soc/qualcomm/sdm845/cbmem.c
new file mode 100644
index 0000000..45cda8f
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/cbmem.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+ return NULL;
+}
diff --git a/src/soc/qualcomm/sdm845/i2c.c b/src/soc/qualcomm/sdm845/i2c.c
new file mode 100644
index 0000000..8ce6f54
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/i2c.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/i2c_simple.h>
+
+int platform_i2c_transfer(unsigned bus, struct i2c_msg *segments,
+ int seg_count)
+{
+ return 0;
+}
diff --git a/src/soc/qualcomm/sdm845/include/soc/gpio.h b/src/soc/qualcomm/sdm845/include/soc/gpio.h
new file mode 100644
index 0000000..9b2a0f4
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/include/soc/gpio.h
@@ -0,0 +1,23 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_QUALCOMM_SDM845_GPIO_H_
+#define _SOC_QUALCOMM_SDM845_GPIO_H_
+
+#include <types.h>
+
+typedef u32 gpio_t;
+
+#endif // _SOC_QUALCOMM_SDM845_GPIO_H_
diff --git a/src/soc/qualcomm/sdm845/include/soc/memlayout.ld b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld
new file mode 100644
index 0000000..a81df2c
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/include/soc/memlayout.ld
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <memlayout.h>
+#include <arch/header.ld>
+
+#define SRAM_XBL_START(addr) SYMBOL(xbl, addr)
+#define SRAM_XBL_END(addr) SYMBOL(exbl, addr)
+
+#define SRAM2_START(addr) SYMBOL(sram2, addr)
+#define SRAM2_END(addr) SYMBOL(esram2, addr)
+
+#define SRAM3_START(addr) SYMBOL(sram3, addr)
+#define SRAM3_END(addr) SYMBOL(esram3, addr)
+
+#define SRAM4_START(addr) SYMBOL(sram4, addr)
+#define SRAM4_END(addr) SYMBOL(esram4, addr)
+
+// SYSTEM_IMEM : 0x14680000 - 0x146C0000
+// BOOT_IMEM : 0x14800000 - 0x14980000
+
+SECTIONS
+{
+ SRAM_START(0x14680000)
+ OVERLAP_VERSTAGE_ROMSTAGE(0x14680000, 95K)
+ SRAM_END(0x1469FC00)
+
+ SRAM2_START(0x146A0000)
+ // This area, used by other firmware in system
+ SRAM2_END(0x146C0000)
+
+ SRAM3_START(0x14800000)
+ // This area, contains PBL shared data & mmu non-cacheable areas
+ SRAM3_END(0x14816000)
+
+ SRAM4_START(0x14816000)
+ BOOTBLOCK(0x14816000, 32K)
+ TTB(0x1481E000, 64K)
+ VBOOT2_WORK(0x1482E000, 16K)
+ STACK(0x14832000, 16K)
+ TIMESTAMP(0x14836000, 1K)
+ PRERAM_CBMEM_CONSOLE(0x14836400, 32K)
+ PRERAM_CBFS_CACHE(0x1483E400, 70K)
+ SRAM_XBL_START(0x1484FC00)
+ // size available is 1217KB
+ // qclib.elf starts at 0x148F2000, 512KB
+ // dcb.elf starts at 0x14972000, 8KB
+ // pmic.elf starts at 0x14974000, 48KB
+ SRAM_XBL_END(0x14980000)
+ SRAM4_END(0x14980000)
+
+ DRAM_START(0x80000000)
+ RAMSTAGE(0x80800000, 128K)
+ SYMBOL(memlayout_cbmem_top, 0xA1000000)
+ POSTRAM_CBFS_CACHE(0xA1000000, 384K)
+}
diff --git a/src/soc/qualcomm/sdm845/soc.c b/src/soc/qualcomm/sdm845/soc.c
new file mode 100644
index 0000000..9f2fbc4
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/soc.c
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/device.h>
+
+static void soc_read_resources(device_t dev)
+{
+
+}
+
+static void soc_init(device_t dev)
+{
+
+}
+
+static struct device_operations soc_ops = {
+ .read_resources = soc_read_resources,
+ .init = soc_init,
+};
+
+static void enable_soc_dev(device_t dev)
+{
+ dev->ops = &soc_ops;
+}
+
+struct chip_operations soc_qualcomm_sdm845_ops = {
+ CHIP_NAME("SOC Qualcomm SDM845")
+ .enable_dev = enable_soc_dev,
+};
diff --git a/src/soc/qualcomm/sdm845/spi.c b/src/soc/qualcomm/sdm845/spi.c
new file mode 100644
index 0000000..175b6cf
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/spi.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <spi-generic.h>
+#include <spi_flash.h>
+
+static int spi_ctrlr_claim_bus(const struct spi_slave *slave)
+{
+ return 0;
+}
+
+static void spi_ctrlr_release_bus(const struct spi_slave *slave)
+{
+
+}
+
+static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout,
+ size_t bytes_out, void *din, size_t bytes_in)
+{
+ return 0;
+}
+
+static const struct spi_ctrlr spi_ctrlr = {
+ .claim_bus = spi_ctrlr_claim_bus,
+ .release_bus = spi_ctrlr_release_bus,
+ .xfer = spi_ctrlr_xfer,
+ .max_xfer_size = 65535,
+};
+
+const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = {
+ {
+ .ctrlr = &spi_ctrlr,
+ .bus_start = 0,
+ .bus_end = 0,
+ },
+};
+
+const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);
diff --git a/src/soc/qualcomm/sdm845/stage_entry.c b/src/soc/qualcomm/sdm845/stage_entry.c
new file mode 100644
index 0000000..4cfa9bd
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/stage_entry.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <symbols.h>
+#include <string.h>
+
+extern u8 _bss[], _ebss[];
+extern void main(void);
+void stage_entry(void);
+
+void stage_entry(void)
+{
+ memset(_bss, 0, (_ebss-_bss));
+ main();
+}
diff --git a/src/soc/qualcomm/sdm845/timer.c b/src/soc/qualcomm/sdm845/timer.c
new file mode 100644
index 0000000..b1df161
--- /dev/null
+++ b/src/soc/qualcomm/sdm845/timer.c
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <timer.h>
+#include <delay.h>
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+
+}
+
+void init_timer(void)
+{
+
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I91226c2bc88dd10bc2590d1689267306763bb63e
Gerrit-Change-Number: 23876
Gerrit-PatchSet: 1
Gerrit-Owner: T.Michael Turney <tturne at codeaurora.org>
Gerrit-Reviewer: mturney mturney <mturney at qualcomm.corp-partner.google.com>
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