[coreboot-gerrit] Change in coreboot[master]: soc/intel/broadwell: Generate ACPI DMAR table

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23821


Change subject: soc/intel/broadwell: Generate ACPI DMAR table
......................................................................

soc/intel/broadwell: Generate ACPI DMAR table

If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.

Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/soc/intel/broadwell/acpi.c
M src/soc/intel/broadwell/chip.c
M src/soc/intel/broadwell/include/soc/acpi.h
3 files changed, 57 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/23821/1

diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c
index a23c8e2..6f89e43 100644
--- a/src/soc/intel/broadwell/acpi.c
+++ b/src/soc/intel/broadwell/acpi.c
@@ -37,6 +37,7 @@
 #include <soc/msr.h>
 #include <soc/pci_devs.h>
 #include <soc/pm.h>
+#include <soc/systemagent.h>
 #include <soc/intel/broadwell/chip.h>
 
 /*
@@ -571,6 +572,56 @@
 	}
 }
 
+static unsigned long acpi_fill_dmar(unsigned long current)
+{
+	struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+	const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
+	const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
+
+	/* iGFX has to be enabled, GFXVTBAR set and in 32-bit space. */
+	if (igfx_dev && igfx_dev->enabled &&
+	    gfx_vtbar && !MCHBAR32(GFXVTBAR + 4)) {
+		const unsigned long tmp = current;
+
+		current += acpi_create_dmar_drhd(current, 0, 0, gfx_vtbar);
+		current += acpi_create_dmar_drhd_ds_pci(current, 0, 2, 0);
+
+		acpi_dmar_drhd_fixup(tmp, current);
+	}
+
+	const unsigned long tmp = current;
+	current += acpi_create_dmar_drhd(current,
+			DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar);
+	current += acpi_create_dmar_drhd_ds_ioapic(current,
+			2, PCH_IOAPIC_PCI_BUS, PCH_IOAPIC_PCI_SLOT, 0);
+	size_t i;
+	for (i = 0; i < 8; ++i)
+		current += acpi_create_dmar_drhd_ds_msi_hpet(current,
+				0, PCH_HPET_PCI_BUS, PCH_HPET_PCI_SLOT, i);
+	acpi_dmar_drhd_fixup(tmp, current);
+
+	return current;
+}
+
+unsigned long northbridge_write_acpi_tables(struct device *const dev,
+					    unsigned long current,
+					    struct acpi_rsdp *const rsdp)
+{
+	/* Create DMAR table only if we have VT-d capability. */
+	const u32 capid0_a = pci_read_config32(dev, CAPID0_A);
+	if (capid0_a & VTD_DISABLE)
+		return current;
+
+	acpi_dmar_t *const dmar = (acpi_dmar_t *)current;
+	printk(BIOS_DEBUG, "ACPI:    * DMAR\n");
+	acpi_create_dmar(dmar, DMAR_INTR_REMAP, acpi_fill_dmar);
+	current += dmar->header.length;
+	current = acpi_align_current(current);
+	acpi_add_table(rsdp, dmar);
+
+	return current;
+}
+
 unsigned long acpi_madt_irq_overrides(unsigned long current)
 {
 	int sci = acpi_sci_irq();
diff --git a/src/soc/intel/broadwell/chip.c b/src/soc/intel/broadwell/chip.c
index 8176c8e..a0ffd5a 100644
--- a/src/soc/intel/broadwell/chip.c
+++ b/src/soc/intel/broadwell/chip.c
@@ -16,6 +16,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <soc/acpi.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
 #include <soc/intel/broadwell/chip.h>
@@ -30,6 +31,9 @@
 	.set_resources    = &pci_domain_set_resources,
 	.scan_bus         = &pci_domain_scan_bus,
 	.ops_pci_bus      = &pci_bus_default_ops,
+#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
+	.write_acpi_tables	= &northbridge_write_acpi_tables,
+#endif
 };
 
 static struct device_operations cpu_bus_ops = {
diff --git a/src/soc/intel/broadwell/include/soc/acpi.h b/src/soc/intel/broadwell/include/soc/acpi.h
index f766dc9..24fe3ae 100644
--- a/src/soc/intel/broadwell/include/soc/acpi.h
+++ b/src/soc/intel/broadwell/include/soc/acpi.h
@@ -29,5 +29,6 @@
 void acpi_fill_in_fadt(acpi_fadt_t *fadt);
 unsigned long acpi_madt_irq_overrides(unsigned long current);
 void acpi_init_gnvs(global_nvs_t *gnvs);
-
+unsigned long northbridge_write_acpi_tables(struct device *dev,
+	unsigned long current, struct acpi_rsdp *rsdp);
 #endif

-- 
To view, visit https://review.coreboot.org/23821
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id7c899954f1bae9d2b48532ca5ee271944f0c5f6
Gerrit-Change-Number: 23821
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180219/f24892b1/attachment.html>