[coreboot-gerrit] Change in coreboot[master]: soc/intel/denverton_ns: Add UART legacy mode with FSP traces

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23623 )

Change subject: soc/intel/denverton_ns: Add UART legacy mode with FSP traces
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Patch Set 3: Verified+1

Build Successful 

https://qa.coreboot.org/job/coreboot-gerrit/67465/ : SUCCESS

https://qa.coreboot.org/job/coreboot-checkpatch/22002/ : SUCCESS


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Id8801e178ffd8eeee78ece07da7bd6b8dbd88538
Gerrit-Change-Number: 23623
Gerrit-PatchSet: 3
Gerrit-Owner: Julien Viard de Galbert <jviarddegalbert at online.net>
Gerrit-Reviewer: FEI WANG <wangfei.jimei at gmail.com>
Gerrit-Reviewer: Julien Viard de Galbert <jviarddegalbert at online.net>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Shine Liu <shine.liu at intel.com>
Gerrit-Reviewer: Vanny E <vanessa.f.eusebio at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Wed, 14 Feb 2018 15:52:09 +0000
Gerrit-HasComments: No
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