[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Switch to common PCR ASL

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/23725


Change subject: soc/intel/skylake: Switch to common PCR ASL
......................................................................

soc/intel/skylake: Switch to common PCR ASL

Using common PCR asl for skylake/kabylake platform.

BUG=None
TEST=None

Change-Id: I99ec7c878adaea439108553c0fac9d5abe1bc248
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/skylake/acpi/pch.asl
D src/soc/intel/skylake/acpi/pcr.asl
2 files changed, 1 insertion(+), 89 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/23725/1

diff --git a/src/soc/intel/skylake/acpi/pch.asl b/src/soc/intel/skylake/acpi/pch.asl
index e40dd6b..0c4decc 100644
--- a/src/soc/intel/skylake/acpi/pch.asl
+++ b/src/soc/intel/skylake/acpi/pch.asl
@@ -39,7 +39,7 @@
 #include "pcie.asl"
 
 /* PCR Access */
-#include "pcr.asl"
+#include <soc/intel/common/acpi/pcr.asl>
 
 /* PMC 0:1f.2 */
 #include "pmc.asl"
diff --git a/src/soc/intel/skylake/acpi/pcr.asl b/src/soc/intel/skylake/acpi/pcr.asl
deleted file mode 100644
index c73830f..0000000
--- a/src/soc/intel/skylake/acpi/pcr.asl
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * Calculate PCR register base at specified PID
- * Arg0 - PCR Port ID
- */
-Method (PCRB, 1, NotSerialized)
-{
-	Return (Add (CONFIG_PCR_BASE_ADDRESS,
-				ShiftLeft (Arg0, PCR_PORTID_SHIFT)))
-}
-
-/*
- * Read a PCR register at specified PID and offset
- * Arg0 - PCR Port ID
- * Arg1 - Register Offset
- */
-Method (PCRR, 2, Serialized)
-{
-	OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
-	Field (PCRD, DWordAcc, NoLock, Preserve)
-	{
-		DATA, 32
-	}
-	Return (DATA)
-}
-
-/*
- * AND a value with PCR register at specified PID and offset
- * Arg0 - PCR Port ID
- * Arg1 - Register Offset
- * Arg2 - Value to AND
- */
-Method (PCRA, 3, Serialized)
-{
-	OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
-	Field (PCRD, DWordAcc, NoLock, Preserve)
-	{
-		DATA, 32
-	}
-	And (DATA, Arg2, DATA)
-
-	/*
-	 * After every write one needs to read an innocuous register
-	 * to ensure the writes are completed for certain ports. This is done
-	 * for all ports so that the callers don't need the per-port knowledge
-	 * for each transaction.
-	 */
-	PCRR (Arg0, Arg1)
-}
-
-/*
- * OR a value with PCR register at specified PID and offset
- * Arg0 - PCR Port ID
- * Arg1 - Register Offset
- * Arg2 - Value to OR
- */
-Method (PCRO, 3, Serialized)
-{
-	OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4)
-	Field (PCRD, DWordAcc, NoLock, Preserve)
-	{
-		DATA, 32
-	}
-	Or (DATA, Arg2, DATA)
-
-	/*
-	 * After every write one needs to read an innocuous register
-	 * to ensure the writes are completed for certain ports. This is done
-	 * for all ports so that the callers don't need the per-port knowledge
-	 * for each transaction.
-	 */
-	PCRR (Arg0, Arg1)
-}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I99ec7c878adaea439108553c0fac9d5abe1bc248
Gerrit-Change-Number: 23725
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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