[coreboot-gerrit] Change in coreboot[master]: soc/intel/common/block: Fix SATA chipset register definitions anomalies

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23589 )

Change subject: soc/intel/common/block: Fix SATA chipset register definitions anomalies
......................................................................


Patch Set 6: Verified-1

Build Failed 

https://qa.coreboot.org/job/coreboot-gerrit/67147/ : ABORTED

https://qa.coreboot.org/job/coreboot-checkpatch/21712/ : SUCCESS


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: Iafed4fe09fe513c8087453ea78364a693e1e8a8a
Gerrit-Change-Number: 23589
Gerrit-PatchSet: 6
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin at chromium.org>
Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan at intel.com>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Hannah Williams <hannah.williams at intel.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Paul Menzel <paulepanter at users.sourceforge.net>
Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi at intel.com>
Gerrit-Reviewer: Subrata Banik <subrata.banik at intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Wed, 07 Feb 2018 06:46:37 +0000
Gerrit-HasComments: No
Gerrit-HasLabels: Yes
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