[coreboot-gerrit] Change in coreboot[master]: cpu/intel/sandybridge: Put stage cache into TSEG

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/23592 )

Change subject: cpu/intel/sandybridge: Put stage cache into TSEG
......................................................................

cpu/intel/sandybridge: Put stage cache into TSEG

TSEG is not accessible in ring 0 after it is locked in
ramstage, in contrast with cbmem which remains accessible. Assuming
SMM does not touch the cache this is a good region to cache stages.

TESTED on Thinkpad X220: on a cold boot the stage cache gets created
and on S3 the cached ramstage gets properly used.

Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/cpu/intel/model_206ax/Kconfig
M src/cpu/intel/model_206ax/Makefile.inc
M src/cpu/intel/model_206ax/model_206ax.h
A src/cpu/intel/model_206ax/stage_cache.c
M src/cpu/intel/smm/gen1/smmrelocate.c
M src/northbridge/intel/sandybridge/sandybridge.h
6 files changed, 64 insertions(+), 1 deletion(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/23592/2
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Ifd8f939416b1712f6e5c74f544a5828745f8c2f2
Gerrit-Change-Number: 23592
Gerrit-PatchSet: 2
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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