[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Implement Sata SOC override as per SPT-PCH

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/23590


Change subject: soc/intel/skylake: Implement Sata SOC override as per SPT-PCH
......................................................................

soc/intel/skylake: Implement Sata SOC override as per SPT-PCH

This patch ensures soc/sata.c correctly translate pci config
offset 0x92 bit 0-2.

Bit 0-2
Port x Enabled (PxE)
0 = Disabled. The Port is in the 'off' state and can't detect any devices.
1 = Enabled. The port can detect devices.

Change-Id: I497e367f4b1dd83130c137965df906abf3b8ae0f
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/soc/intel/skylake/Makefile.inc
A src/soc/intel/skylake/sata.c
2 files changed, 59 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/23590/1

diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index ef95cf7..0c7355a 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -58,6 +58,7 @@
 ramstage-y += pmc.c
 ramstage-y += pmutil.c
 ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
+ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SATA) += sata.c
 ramstage-y += sd.c
 ramstage-y += smmrelocate.c
 ramstage-y += spi.c
diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c
new file mode 100644
index 0000000..d7b6215
--- /dev/null
+++ b/src/soc/intel/skylake/sata.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2018 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <intelblocks/sata.h>
+#include <soc/pci_devs.h>
+
+#define SATA_ABAR_PORT_IMPLEMENTED	0x0c
+#define SATA_PCI_CFG_PORT_CTL_STS	0x92
+
+static void *get_ahci_bar(device_t dev)
+{
+	uintptr_t bar;
+
+	bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
+	return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK);
+}
+
+/*
+ * SATA Port control and Status. By default, the SATA ports are set (by HW)
+ * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial
+ * power on reset. When enabled by software as per SATA port mapping,
+ * the ports can transition between the on, partial and slumber states
+ * and can detect devices. When disabled, the port is in the off state and
+ * can't detect any devices.
+ */
+void sata_soc_final(device_t dev)
+{
+	void *ahcibar = get_ahci_bar(dev);
+	u32 port_impl, temp;
+
+	/* Set Bus Master */
+	temp = pci_read_config32(dev, PCI_COMMAND);
+	pci_write_config32(dev, PCI_COMMAND, temp | PCI_COMMAND_MASTER);
+
+	/* Read Ports Implemented (GHC_PI) */
+	port_impl = read32(ahcibar + SATA_ABAR_PORT_IMPLEMENTED) & 0x07;
+	/* Port enable */
+	temp = pci_read_config32(dev, SATA_PCI_CFG_PORT_CTL_STS);
+	temp |= port_impl;
+	pci_write_config32(dev, SATA_PCI_CFG_PORT_CTL_STS, temp);
+}

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I497e367f4b1dd83130c137965df906abf3b8ae0f
Gerrit-Change-Number: 23590
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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