[coreboot-gerrit] Change in coreboot[master]: google/lars: update device properties for Nuvoton codec

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/23567


Change subject: google/lars: update device properties for Nuvoton codec
......................................................................

google/lars: update device properties for Nuvoton codec

Adapted from Chromium commit:
848ee3a [Lars: Add device properties for Nuvoton codec]

Update sar-threshold, sar-compare-time, sar-sampling-time
properties to match values in lars' Chromium branch.

Adaptation needed to account for parameters having moved
from mainboard.asl to devicetree in upstream tree.

Original-Change-Id: Id0c28e50406a29e6f33d04ca78fd2a3e3974fa90
Original-Signed-off-by: David Wu <David_Wu at quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin at chromium.org>
Original-Reviewed-by: Benson Leung <bleung at chromium.org>
Original-Tested-by: David Wu <david_wu at quantatw.com>

Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3
Signed-off-by: Matt DeVillier <matt.devillier at gmail.com>
---
M src/mainboard/google/lars/devicetree.cb
1 file changed, 4 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/23567/1

diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index 99522cb..64f2a61 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -233,14 +233,14 @@
 				register "vref_impedance" = "2"      # 125kOhm
 				register "micbias_voltage" = "6"     # 2.754
 				register "sar_threshold_num" = "4"
-				register "sar_threshold[0]" = "0x0a"
-				register "sar_threshold[1]" = "0x14"
+				register "sar_threshold[0]" = "0x08"
+				register "sar_threshold[1]" = "0x12"
 				register "sar_threshold[2]" = "0x26"
 				register "sar_threshold[3]" = "0x73"
 				register "sar_hysteresis" = "0"
 				register "sar_voltage" = "6"
-				register "sar_compare_time" = "0"     # 500ns
-				register "sar_sampling_time" = "0"    # 2us
+				register "sar_compare_time" = "1"     # 1us
+				register "sar_sampling_time" = "1"    # 4us
 				register "short_key_debounce" = "3"   # 30ms
 				register "jack_insert_debounce" = "7" # 512ms
 				register "jack_eject_debounce" = "0"

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3
Gerrit-Change-Number: 23567
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier at gmail.com>
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