[coreboot-gerrit] Change in ...coreboot[master]: mb/google/hatch: Enable LPC IO decode range for EC

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30417


Change subject: mb/google/hatch: Enable LPC IO decode range for EC
......................................................................

mb/google/hatch: Enable LPC IO decode range for EC

Add support to enable IO decode on below ranges:
1. 0x200-020F: EC host command range.
2. 0x800-0x8FF: EC host command args and params.
3. 0x900-0x9ff: EC memory map range.

Change-Id: Id97424c4921a3f6afa1a69a9de637a90158c55d4
Signed-off-by: Aamir Bohra <aamir.bohra at intel.com>
---
M src/mainboard/google/hatch/variants/baseboard/devicetree.cb
1 file changed, 6 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/30417/1

diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
index 2e171b0..3cdc3e0 100644
--- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb
@@ -10,6 +10,12 @@
 	register "gpe0_dw1" = "PMC_GPP_C"
 	register "gpe0_dw2" = "PMC_GPP_D"
 
+	# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+	register "gen1_dec" = "0x00fc0801"
+	register "gen2_dec" = "0x000c0201"
+	# EC memory map range is 0x900-0x9ff
+	register "gen3_dec" = "0x00fc0901"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Id97424c4921a3f6afa1a69a9de637a90158c55d4
Gerrit-Change-Number: 30417
Gerrit-PatchSet: 1
Gerrit-Owner: Aamir Bohra <aamir.bohra at intel.com>
Gerrit-MessageType: newchange
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