[coreboot-gerrit] Change in ...coreboot[master]: nb/intel/haswell: Add support for PCIe graphics

[Tristan Corrick (Code Review)]

Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/30272

to look at the new patch set (#6).

Change subject: nb/intel/haswell: Add support for PCIe graphics
......................................................................

nb/intel/haswell: Add support for PCIe graphics

There are two different paths added for PEG link training.

*The first path*: If it's okay for the IGD to be disabled, the link
training is done in early romstage. The MRC will then set (and lock)
GGC, and, if there is a device of VGA class present in a PEG slot,
disable the IGD:

	Before the MRC: GGC = 0x0208, DEVEN = 0x00000039.
	After the MRC:  GGC = 0x0003, DEVEN = 0x00000029.

*The second path*: If the IGD needs to be kept enabled, the link
training is done in ramstage. This is because the MRC will always
disable the IGD if there is a device of VGA class in a PEG slot, but
it can't see the device until link training is done.

The second path can, unfortunately, lead to an increase in boot time, as
the training needs to be complete before the PEG bus is scanned. When
there are multiple PEG devices, the training occurs in parallel, limiting
the impact on boot time.

The worst case occurs when `CONFIG_ONBOARD_VGA_IS_PRIMARY` is set (which
is not the default), the IGD is enabled, and there is an unpopulated PEG
slot. This leads to the PEG training always hitting the timeout, which
is 100 ms of wasted time.

Only PEG2 is supported. An extra (unknown) training sequence is said to
be needed for PEG3.

The ACPI _PRT method is not yet generated, so legacy interrupt routing
doesn't work for devices with multiple functions.

Tested on an ASRock H81M-HDS. Using an x1 PCIe card in the PEG slot
works fine. Using a Radeon HD 6450 graphics card also works under
GNU/Linux, both using the display from the Radeon HD 6450, and when the
IGD is used for display output and `DRI_PRIME=1` is set.

Link training for the x1 PCIe card takes about 30 ms. For the Radeon
HD 6450, it's about 15 ms.

Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e
Signed-off-by: Tristan Corrick <tristan at corrick.kiwi>
---
M src/northbridge/intel/haswell/Makefile.inc
M src/northbridge/intel/haswell/early_init.c
M src/northbridge/intel/haswell/haswell.h
A src/northbridge/intel/haswell/peg.c
4 files changed, 183 insertions(+), 6 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/30272/6
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I786ecb6eccad8de89778af7e736ed664323e220e
Gerrit-Change-Number: 30272
Gerrit-PatchSet: 6
Gerrit-Owner: Tristan Corrick <tristan at corrick.kiwi>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Tristan Corrick <tristan at corrick.kiwi>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: newpatchset
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