[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Program internal SVID/SSID

[Lijian Zhao (Code Review)]

Lijian Zhao has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29651 )

Change subject: soc/intel/cannonlake: Program internal SVID/SSID
......................................................................


Patch Set 8:

> Patch Set 7:
> 
> > But XHCI lock down is part of BIOS programming guide that directly from chipset design guide, FSP will follow that documentation and stay as is.
> 
> In what FSP phase is that done? Subsystem ids are set in BS_DEV_ENABLE on the coreboot side. But I've just learned that FSP's AFTER_PCI_ENUM is called before BS_DEV_ENABLE... why is that the case? seems wrong to me.

I didn't see the code yet, but yes the following is what's current FSP entry is.

https://github.com/coreboot/coreboot/blob/master/src/drivers/intel/fsp2_0/notify.c

BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fsp_notify_dummy,
						(void *) AFTER_PCI_ENUM);
BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, fsp_notify_dummy,
						(void *) READY_TO_BOOT);
BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, fsp_notify_dummy,
						(void *) READY_TO_BOOT);


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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I25e22313fd99479f1a2f68636a2eab83126ca488
Gerrit-Change-Number: 29651
Gerrit-PatchSet: 8
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Jairaj Arava <jairaj.arava at intel.com>
Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula at intel.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
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