[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Use meaningful SATA mode

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30095 )

Change subject: mb/google/sarien: Use meaningful SATA mode
......................................................................

mb/google/sarien: Use meaningful SATA mode

Define SATA mode to AHCI mode instead of 0, make devicetree more
readable.

BUG=N/A

Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
Reviewed-on: https://review.coreboot.org/c/30095
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie at chromium.org>
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Duncan Laurie: Looks good to me, approved



diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 18bd155..acdb623 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -17,7 +17,7 @@
 	register "SaGv" = "3"
 	register "HeciEnabled" = "1"
 	register "SataSalpSupport" = "1"
-	register "SataMode" = "0"
+	register "SataMode" = "Sata_AHCI"
 	register "SataPortsEnable[2]" = "1"
 	register "SataPortsDevSlp[2]" = "1"
 	register "InternalGfx" = "1"
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 771bec2..2800ff5 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -17,7 +17,7 @@
 	register "SaGv" = "3"
 	register "HeciEnabled" = "1"
 	register "SataSalpSupport" = "1"
-	register "SataMode" = "0"
+	register "SataMode" = "Sata_AHCI"
 	register "SataPortsEnable[0]" = "1"
 	register "SataPortsEnable[1]" = "1"
 	register "SataPortsEnable[2]" = "1"

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I903545d9487c1409f9008407fe5bee6aa4959b98
Gerrit-Change-Number: 30095
Gerrit-PatchSet: 3
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-MessageType: merged
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