[coreboot-gerrit] Change in ...coreboot[master]: mb/google/kahlee: Remove board_id check for Liara 2T timings

[Martin Roth (Code Review)]

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30285


Change subject: mb/google/kahlee: Remove board_id check for Liara 2T timings
......................................................................

mb/google/kahlee: Remove board_id check for Liara 2T timings

Use 2T memory timings on Liara for all board IDs.

BUG=b:116082728
TEST=Build & boot on Liara

Change-Id: I5814e63db35cf7761f4f20792b0f3cf4120a1b60
Signed-off-by: Martin Roth <martinroth at google.com>
---
M src/mainboard/google/kahlee/OemCustomize.c
1 file changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30285/1

diff --git a/src/mainboard/google/kahlee/OemCustomize.c b/src/mainboard/google/kahlee/OemCustomize.c
index fc8ff32..ce70b8d 100644
--- a/src/mainboard/google/kahlee/OemCustomize.c
+++ b/src/mainboard/google/kahlee/OemCustomize.c
@@ -38,7 +38,7 @@
 				0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00),
 	PSO_END
 };
-/* TODO: Remove when no longer needed */
+/* Liara-specific 2T memory configuration */
 static const PSO_ENTRY DDR4LiaraMemoryConfiguration[] = {
 	DRAM_TECHNOLOGY(ANY_SOCKET, DDR4_TECHNOLOGY),
 	NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, DIMMS_PER_CHANNEL),
@@ -58,7 +58,7 @@
 
 void OemPostParams(AMD_POST_PARAMS *PostParams)
 {
-	if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 5))
+	if (IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA))
 		PostParams->MemConfig.PlatformMemoryConfiguration =
 			(PSO_ENTRY *)DDR4LiaraMemoryConfiguration;
 	else

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5814e63db35cf7761f4f20792b0f3cf4120a1b60
Gerrit-Change-Number: 30285
Gerrit-PatchSet: 1
Gerrit-Owner: Martin Roth <martinroth at google.com>
Gerrit-MessageType: newchange
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