[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/braswell/linclude/soc/device_nvs.h: Fix typo

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30277


Change subject: soc/intel/braswell/linclude/soc/device_nvs.h: Fix typo
......................................................................

soc/intel/braswell/linclude/soc/device_nvs.h: Fix typo

Use 'BAR 1' for the bar1 structure fields.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I1d1278f549fc8a2f3e743e2e2019d3e5f7005614
Signed-off-by: Frans Hendriks <fhendriks at eltan.com>
---
M src/soc/intel/braswell/include/soc/device_nvs.h
1 file changed, 2 insertions(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/30277/1

diff --git a/src/soc/intel/braswell/include/soc/device_nvs.h b/src/soc/intel/braswell/include/soc/device_nvs.h
index e98337c..1b4f3ba 100644
--- a/src/soc/intel/braswell/include/soc/device_nvs.h
+++ b/src/soc/intel/braswell/include/soc/device_nvs.h
@@ -3,6 +3,7 @@
  *
  * Copyright (C) 2013 Google Inc.
  * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2018 Eltan B.V.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -49,7 +50,7 @@
 	u32	scc_bar0[3];
 	u32	lpe_bar0;
 
-	/* BAR 0 */
+	/* BAR 1 */
 	u32	lpss_bar1[14];
 	u32	scc_bar1[3];
 	u32	lpe_bar1;

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I1d1278f549fc8a2f3e743e2e2019d3e5f7005614
Gerrit-Change-Number: 30277
Gerrit-PatchSet: 1
Gerrit-Owner: Frans Hendriks <fhendriks at eltan.com>
Gerrit-MessageType: newchange
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