[coreboot-gerrit] Change in ...coreboot[master]: smsc/sch5147: Implement ACPI handling of a few LDN
Arthur Heymans (Code Review)
gerrit at coreboot.org
Sat Dec 15 20:07:53 CET 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30240
Change subject: smsc/sch5147: Implement ACPI handling of a few LDN
......................................................................
smsc/sch5147: Implement ACPI handling of a few LDN
Change-Id: Ide30a7396b6248e2037041e177dc8514533718a4
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl
A src/superio/smsc/sch5147/acpi/superio.asl
2 files changed, 258 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/30240/1
diff --git a/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl b/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl
index 48e70a7..8902579 100644
--- a/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl
+++ b/src/mainboard/lenovo/thinkcentre_a58/acpi/superio.asl
@@ -1 +1,25 @@
-/* TODO */
\ No newline at end of file
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef SCH5147_SHOW_UARTA
+#undef SCH5147_SHOW_UARTB
+#undef SCH5147_SHOW_KBC
+#undef SCH5147_SHOW_HWMON
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define SCH5147_SHOW_UARTA
+#define SCH5147_SHOW_UARTB
+#define SCH5147_SHOW_KBC
+#include <superio/smsc/sch5147/acpi/superio.asl>
diff --git a/src/superio/smsc/sch5147/acpi/superio.asl b/src/superio/smsc/sch5147/acpi/superio.asl
new file mode 100644
index 0000000..f24db60
--- /dev/null
+++ b/src/superio/smsc/sch5147/acpi/superio.asl
@@ -0,0 +1,233 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Include this file into a mainboard's DSDT _SB device tree and it will
+ * expose the W83627DHG SuperIO and some of its functionality.
+ *
+ * It allows the change of IO ports, IRQs and DMA settings on logical
+ * devices, disabling and reenabling logical devices and controlling power
+ * saving mode on logical devices or the whole chip.
+ *
+ * LDN State
+ * 0x0 FDC Not implemented
+ * 0x3 PP Not implemented
+ * 0x4 UARTA Implemented
+ * 0x5 UARTB Implemented
+ * 0x7 KBC Implemented
+ * 0xa Runtime reg Not implemented
+ *
+ * Controllable through preprocessor defines:
+ * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0)
+ * SUPERIO_PNP_BASE I/o address of the first PnP configuration register
+ * SCH5147_SHOW_UARTA If defined, UARTA will be exposed.
+ * SCH5147_SHOW_UARTB If defined, UARTB will be exposed.
+ * SCH5147_SHOW_KBC If defined, the KBC will be exposed.
+ */
+
+#undef SUPERIO_CHIP_NAME
+#define SUPERIO_CHIP_NAME SCH5147
+#include <superio/acpi/pnp.asl>
+
+#undef PNP_DEFAULT_PSC
+#define PNP_DEFAULT_PSC Return (0) /* no power management */
+
+Device(SUPERIO_DEV) {
+ Name (_HID, EisaId("PNP0A05"))
+ Name (_STR, Unicode("SMSC SCH5147 Super I/O"))
+ Name (_UID, SUPERIO_UID(SUPERIO_DEV,))
+
+ /* Mutex for accesses to the configuration ports */
+ Mutex(CRMX, 1)
+
+ /* SuperIO configuration ports */
+ OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02)
+ Field (CREG, ByteAcc, NoLock, Preserve)
+ {
+ PNP_ADDR_REG, 8,
+ PNP_DATA_REG, 8
+ }
+ IndexField (ADDR, DATA, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ PNP_LOGICAL_DEVICE, 8, /* Logical device selector */
+
+ Offset (0x30),
+ PNP_DEVICE_ACTIVE, 1, /* Logical device activation */
+
+ Offset (0x60),
+ PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */
+ PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */
+ Offset (0x62),
+ PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */
+ PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */
+
+ Offset (0x70),
+ PNP_IRQ0, 8, /* First IRQ */
+ Offset (0x72),
+ PNP_IRQ1, 8, /* Second IRQ */
+
+ Offset (0x74),
+ PNP_DMA0, 8, /* DMA */
+ }
+
+ Method (_CRS)
+ {
+ /* Announce the used i/o ports to the OS */
+ Return (ResourceTemplate () {
+ IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02)
+ })
+ }
+
+ #undef PNP_ENTER_MAGIC_1ST
+ #undef PNP_ENTER_MAGIC_2ND
+ #undef PNP_ENTER_MAGIC_3RD
+ #undef PNP_ENTER_MAGIC_4TH
+ #undef PNP_EXIT_MAGIC_1ST
+ #undef PNP_EXIT_SPECIAL_REG
+ #undef PNP_EXIT_SPECIAL_VAL
+ #define PNP_ENTER_MAGIC_1ST 0x55
+ #define PNP_EXIT_MAGIC_1ST 0xaa
+ #include <superio/acpi/pnp_config.asl>
+
+#ifdef SCH5147_SHOW_UARTA
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 4
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef SCH5147_SHOW_UARTB
+ #undef SUPERIO_UART_LDN
+ #undef SUPERIO_UART_DDN
+ #undef SUPERIO_UART_PM_REG
+ #undef SUPERIO_UART_PM_VAL
+ #undef SUPERIO_UART_PM_LDN
+ #define SUPERIO_UART_LDN 5
+ #include <superio/acpi/pnp_uart.asl>
+#endif
+
+#ifdef SCH5147_SHOW_KBC
+ /* we can't read back the IO resources so hardcode them */
+ #define SUPERIO_KBC_LDN 7
+Device (SUPERIO_ID(KBD, SUPERIO_KBC_LDN)) {
+ Name (_HID, EisaId ("PNP0303"))
+ Name (_UID, SUPERIO_UID(KBD, SUPERIO_KBC_LDN))
+
+ Method (_STA)
+ {
+ PNP_GENERIC_STA(SUPERIO_KBC_LDN)
+ }
+
+ Method (_DIS)
+ {
+ ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
+ Store (Zero, PNP_DEVICE_ACTIVE)
+ EXIT_CONFIG_MODE ()
+ #if defined(SUPERIO_KBC_PS2LDN)
+ Notify (SUPERIO_ID(PS2, SUPERIO_KBC_PS2LDN), 1)
+ #elif defined(SUPERIO_KBC_PS2M)
+ Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1)
+ #endif
+ }
+
+ Method (_PSC) {
+ PNP_DEFAULT_PSC
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (CRS, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags (IR0) {}
+ })
+ ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
+ PNP_READ_IRQ(PNP_IRQ0, CRS, IR0)
+ EXIT_CONFIG_MODE ()
+ Return (CRS)
+ }
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFn (0,0) {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ }
+ EndDependentFn()
+ })
+
+ Method (_SRS, 1, Serialized)
+ {
+ Name (TMPL, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags (IR0) {}
+ })
+ ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
+ PNP_WRITE_IRQ(PNP_IRQ0, Arg0, IR0)
+ Store (One, PNP_DEVICE_ACTIVE)
+ EXIT_CONFIG_MODE ()
+ Notify (SUPERIO_ID(PS2, SUPERIO_KBC_LDN), 1)
+ }
+}
+
+Device (SUPERIO_ID(PS2, SUPERIO_KBC_LDN)) {
+ Name (_HID, EisaId ("PNP0F13"))
+ Name (_UID, SUPERIO_UID(PS2, SUPERIO_KBC_LDN))
+
+ Method (_STA)
+ {
+ Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._STA ())
+ }
+
+ Method (_PSC) {
+ Return (^^SUPERIO_ID(KBD, SUPERIO_KBC_LDN)._PSC ())
+ }
+
+ Method (_CRS, 0, Serialized)
+ {
+ Name (CRS, ResourceTemplate () {
+ IRQNoFlags (IR1) {}
+ })
+ ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
+ PNP_READ_IRQ(PNP_IRQ1, CRS, IR1)
+ EXIT_CONFIG_MODE ()
+ Return (CRS)
+ }
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFn (0,0) {
+ IRQNoFlags () {12}
+ }
+ EndDependentFn()
+ })
+
+ Method (_SRS, 1, Serialized)
+ {
+ Name (TMPL, ResourceTemplate () {
+ IRQNoFlags (IR1) {}
+ })
+ ENTER_CONFIG_MODE (SUPERIO_KBC_LDN)
+ PNP_WRITE_IRQ(PNP_IRQ1, Arg0, IR1)
+ EXIT_CONFIG_MODE ()
+ }
+}
+
+#endif
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ide30a7396b6248e2037041e177dc8514533718a4
Gerrit-Change-Number: 30240
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-MessageType: newchange
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