[coreboot-gerrit] Change in ...coreboot[master]: drivers/generic: Add PCIe bridge helper

[Richard Spiegel (Code Review)]

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30215 )

Change subject: drivers/generic: Add PCIe bridge helper
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Patch Set 4:

(6 comments)

> Patch Set 4:
> 
> (4 comments)
> 
> Do you really need this in all its complexity? Many things seem overkill and the ramstage part doesn't fit into our current driver model.

Yes, I need. I need to access devices behind a bridge, before and after PCI enumeration. The only complexity is the possibility to access/program all the BARs. Currently, I only need BAR0.
I could just force a particular range of addresses, but it does not add much complexity to allow user define a preferred range.

https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c 
File src/drivers/generic/temp_pcie_bridge/bridge_rom.c:

https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c@28 
PS4, Line 28: 	outl(reg_2_cf8(dev, reg), 0xCF8);
> back to the early 2000s? why not use the existing access functions?
Existing access functions assume bus 0. They don't work with bus 1, which I'll use as I need to access a device behind a bridge before PCI enumeration.


https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c@66 
PS4, Line 66: 		value &= start;
> potentially aligns `start` down
It does not matter. I just need to assign a base address to one or more BAR registers. I don't care about alignment or holes... it's just temporary assignment, destroyed soon after I access the devices behind the bridge.


https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c@79 
PS4, Line 79: 	pci_write32(dev, TEMP_BASE(number), value);
> missing write to upper part of potential 64-bit resource
If you see the code, I'm forcing 32-bit resource, as it's temporary anyway.


https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c@80 
PS4, Line 80: 	command |= PCI_COMMAND_MASTER;
> wtf? did I miss something and this is required for host initiated i/o?
I'm programming a device behind a bridge, before PCI initialization. So yes, it's needed.


https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c@180 
PS4, Line 180: pci_write_config32
Should be pci_write32 as it's bus 1.


https://review.coreboot.org/#/c/30215/4/src/drivers/generic/temp_pcie_bridge/bridge_rom.c@181 
PS4, Line 181: pci_write_config32
Should be pci_write8, as it's bus 1.



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iaec1fcc4f8db8c3b4cfd3786d3ff589dc9cb22f5
Gerrit-Change-Number: 30215
Gerrit-PatchSet: 4
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
Gerrit-Reviewer: Daniel Kurtz <djkurtz at google.com>
Gerrit-Reviewer: Martin Roth <martinroth at google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: Patrick Rudolph <siro at das-labor.org>
Gerrit-Reviewer: Raul Rangel <rrangel at chromium.org>
Gerrit-Reviewer: Richard Spiegel <richard.spiegel at silverbackltd.com>
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