[coreboot-gerrit] Change in ...coreboot[master]: mb/google/hatch: Creating skeleton directories and files
Shelley Chen (Code Review)
gerrit at coreboot.org
Tue Dec 11 17:12:47 CET 2018
Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30169
Change subject: mb/google/hatch: Creating skeleton directories and files
......................................................................
mb/google/hatch: Creating skeleton directories and files
Creating skeleton files and directories in mainboard for the new Hatch
board. This is to facilitate development for different parties
involved.
BUG=None
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448
Signed-off-by: Shelley Chen <shchen at google.com>
---
A src/mainboard/google/hatch/Kconfig
A src/mainboard/google/hatch/Kconfig.name
A src/mainboard/google/hatch/Makefile.inc
A src/mainboard/google/hatch/acpi_tables.c
A src/mainboard/google/hatch/board_info.txt
A src/mainboard/google/hatch/bootblock.c
A src/mainboard/google/hatch/chromeos.c
A src/mainboard/google/hatch/chromeos.fmd
A src/mainboard/google/hatch/dsdt.asl
A src/mainboard/google/hatch/ramstage.c
A src/mainboard/google/hatch/romstage.c
A src/mainboard/google/hatch/smihandler.c
A src/mainboard/google/hatch/variants/baseboard/Makefile.inc
A src/mainboard/google/hatch/variants/baseboard/gpio.c
A src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/hatch/variants/hatch/Makefile.inc
A src/mainboard/google/hatch/variants/hatch/gpio.c
A src/mainboard/google/hatch/variants/hatch/include/variant/ec.h
A src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h
A src/mainboard/google/hatch/variants/hatch/overridetree.cb
21 files changed, 652 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/30169/1
diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
new file mode 100644
index 0000000..1028f2f
--- /dev/null
+++ b/src/mainboard/google/hatch/Kconfig
@@ -0,0 +1,78 @@
+
+config BOARD_GOOGLE_BASEBOARD_HATCH
+ def_bool n
+ select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_I2C_GENERIC
+ select DRIVERS_I2C_HID
+ select DRIVERS_SPI_ACPI
+ select EC_GOOGLE_CHROMEEC
+ select GENERIC_SPD_BIN
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_I2C_TPM_CR50
+ select MAINBOARD_HAS_TPM2
+ select SOC_INTEL_CANNONLAKE_MEMCFG_INIT
+ select SOC_INTEL_COMMON_ACPI_EC_PTS_WAK
+ select SOC_INTEL_COFFEELAKE
+ select SPD_READ_BY_WORD
+ select SYSTEM_TYPE_LAPTOP
+ select TPM2
+
+if BOARD_GOOGLE_BASEBOARD_HATCH
+
+config CHROMEOS
+ bool
+ default y
+ select GBB_FLAG_FORCE_DEV_SWITCH_ON
+ select GBB_FLAG_FORCE_DEV_BOOT_USB
+ select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+ select GBB_FLAG_FORCE_MANUAL_RECOVERY
+
+config DIMM_MAX
+ int
+ default 2
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "HATCH TEST 1823" if BOARD_GOOGLE_HATCH
+
+config MAINBOARD_DIR
+ string
+ default "google/hatch"
+
+config MAINBOARD_FAMILY
+ string
+ default "Google_Hatch" if BOARD_GOOGLE_HATCH
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Hatch" if BOARD_GOOGLE_HATCH
+
+config MAINBOARD_VENDOR
+ string
+ default "Google"
+
+config MAX_CPUS
+ int
+ default 8
+
+config VARIANT_DIR
+ string
+ default "hatch" if BOARD_GOOGLE_HATCH
+
+config DEVICETREE
+ string
+ default "variants/${CONFIG_VARIANT_DIR}/overridetree.cb"
+
+config VBOOT
+ select HAS_RECOVERY_MRC_CACHE
+ select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
+ select VBOOT_LID_SWITCH
+
+endif # BOARD_GOOGLE_BASEBOARD_HATCH
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name
new file mode 100644
index 0000000..79edb63
--- /dev/null
+++ b/src/mainboard/google/hatch/Kconfig.name
@@ -0,0 +1,5 @@
+comment "Hatch"
+
+config BOARD_GOOGLE_HATCH
+ bool "-> Hatch"
+ select BOARD_GOOGLE_BASEBOARD_HATCH
diff --git a/src/mainboard/google/hatch/Makefile.inc b/src/mainboard/google/hatch/Makefile.inc
new file mode 100644
index 0000000..54e4281
--- /dev/null
+++ b/src/mainboard/google/hatch/Makefile.inc
@@ -0,0 +1,33 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2018 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+
+ramstage-y += ramstage.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-y += romstage.c
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+subdirs-y += variants/$(VARIANT_DIR)
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
diff --git a/src/mainboard/google/hatch/acpi_tables.c b/src/mainboard/google/hatch/acpi_tables.c
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/google/hatch/acpi_tables.c
diff --git a/src/mainboard/google/hatch/board_info.txt b/src/mainboard/google/hatch/board_info.txt
new file mode 100644
index 0000000..4e12c96
--- /dev/null
+++ b/src/mainboard/google/hatch/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Google
+Board name: Hatch
+Category: laptop
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/google/hatch/bootblock.c b/src/mainboard/google/hatch/bootblock.c
new file mode 100644
index 0000000..d349e587
--- /dev/null
+++ b/src/mainboard/google/hatch/bootblock.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+#include <ec/ec.h>
+#include <soc/gpio.h>
+
+static void early_config_gpio(void)
+{
+ const struct pad_config *early_gpio_table;
+ size_t num_gpios = 0;
+
+ early_gpio_table = variant_early_gpio_table(&num_gpios);
+ gpio_configure_pads(early_gpio_table, num_gpios);
+}
+
+void bootblock_mainboard_init(void)
+{
+ early_config_gpio();
+}
diff --git a/src/mainboard/google/hatch/chromeos.c b/src/mainboard/google/hatch/chromeos.c
new file mode 100644
index 0000000..644c247
--- /dev/null
+++ b/src/mainboard/google/hatch/chromeos.c
@@ -0,0 +1,82 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <ec/google/chromeec/ec.h>
+#include <gpio.h>
+#include <rules.h>
+#include <soc/gpio.h>
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {-1, ACTIVE_HIGH, 0, "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+static int cros_get_gpio_value(int type)
+{
+ const struct cros_gpio *cros_gpios;
+ size_t i, num_gpios = 0;
+
+ cros_gpios = variant_cros_gpios(&num_gpios);
+
+ for (i = 0; i < num_gpios; i++) {
+ const struct cros_gpio *gpio = &cros_gpios[i];
+ if (gpio->type == type) {
+ int state = gpio_get(gpio->gpio_num);
+ if (gpio->polarity == CROS_GPIO_ACTIVE_LOW)
+ return !state;
+ else
+ return state;
+ }
+ }
+ return 0;
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ const struct cros_gpio *cros_gpios;
+ size_t num_gpios = 0;
+
+ cros_gpios = variant_cros_gpios(&num_gpios);
+
+ chromeos_acpi_gpio_generate(cros_gpios, num_gpios);
+}
+
+int get_write_protect_state(void)
+{
+ return cros_get_gpio_value(CROS_GPIO_WP);
+}
+
+int get_recovery_mode_switch(void)
+{
+ return cros_get_gpio_value(CROS_GPIO_REC);
+}
+
+int get_lid_switch(void)
+{
+ return 1;
+}
diff --git a/src/mainboard/google/hatch/chromeos.fmd b/src/mainboard/google/hatch/chromeos.fmd
new file mode 100644
index 0000000..6631769
--- /dev/null
+++ b/src/mainboard/google/hatch/chromeos.fmd
@@ -0,0 +1,46 @@
+FLASH at 0xfe000000 0x2000000 {
+ SI_ALL at 0x0 0x1000000 {
+ SI_DESC at 0x0 0x1000
+ SI_EC at 0x1000 0x100000
+ SI_GBE at 0x101000 0x2000
+ SI_ME at 0x103000 0xefd000
+ }
+ SI_BIOS at 0x1000000 0x1000000 {
+ RW_SECTION_A at 0x0 0x280000 {
+ VBLOCK_A at 0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0x26ffc0
+ RW_FWID_A at 0x27ffc0 0x40
+ }
+ RW_SECTION_B at 0x280000 0x280000 {
+ VBLOCK_B at 0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0x26ffc0
+ RW_FWID_B at 0x27ffc0 0x40
+ }
+ RW_MISC at 0x500000 0x30000 {
+ UNIFIED_MRC_CACHE at 0x0 0x20000 {
+ RECOVERY_MRC_CACHE at 0x0 0x10000
+ RW_MRC_CACHE at 0x10000 0x10000
+ }
+ RW_ELOG at 0x20000 0x4000
+ RW_SHARED at 0x24000 0x4000 {
+ SHARED_DATA at 0x0 0x2000
+ VBLOCK_DEV at 0x2000 0x2000
+ }
+ RW_VPD at 0x28000 0x2000
+ RW_NVRAM at 0x2a000 0x6000
+ }
+ CONSOLE at 0x530000 0x20000
+ RW_LEGACY(CBFS)@0x550000 0x6b0000
+ WP_RO at 0xc00000 0x400000 {
+ RO_VPD at 0x0 0x4000
+ RO_UNUSED at 0x4000 0xc000
+ RO_SECTION at 0x10000 0x3f0000 {
+ FMAP at 0x0 0x800
+ RO_FRID at 0x800 0x40
+ RO_FRID_PAD at 0x840 0x7c0
+ GBB at 0x1000 0xef000
+ COREBOOT(CBFS)@0xf0000 0x300000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/hatch/dsdt.asl b/src/mainboard/google/hatch/dsdt.asl
new file mode 100644
index 0000000..61d0e86
--- /dev/null
+++ b/src/mainboard/google/hatch/dsdt.asl
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <variant/ec.h>
+
+#include <arch/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, /* DSDT revision: ACPI v2.0 and up */
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 /* OEM revision */
+)
+{
+}
diff --git a/src/mainboard/google/hatch/ramstage.c b/src/mainboard/google/hatch/ramstage.c
new file mode 100644
index 0000000..0027627
--- /dev/null
+++ b/src/mainboard/google/hatch/ramstage.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <soc/ramstage.h>
+#include <variant/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params)
+{
+ const struct pad_config *gpio_table;
+ size_t num_gpios;
+
+ gpio_table = variant_base_gpio_table(&num_gpios);
+ gpio_configure_pads(gpio_table, num_gpios);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/google/hatch/romstage.c b/src/mainboard/google/hatch/romstage.c
new file mode 100644
index 0000000..ecc8f3c
--- /dev/null
+++ b/src/mainboard/google/hatch/romstage.c
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/cnl_memcfg_init.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd)
+{
+}
diff --git a/src/mainboard/google/hatch/smihandler.c b/src/mainboard/google/hatch/smihandler.c
new file mode 100644
index 0000000..f8f43eb
--- /dev/null
+++ b/src/mainboard/google/hatch/smihandler.c
@@ -0,0 +1,14 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
diff --git a/src/mainboard/google/hatch/variants/baseboard/Makefile.inc b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000..dffacbb
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/baseboard/Makefile.inc
@@ -0,0 +1,7 @@
+bootblock-y += gpio.c
+
+romstage-y += gpio.c
+
+ramstage-y += gpio.c
+
+verstage-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c
new file mode 100644
index 0000000..a0ac059
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c
@@ -0,0 +1,54 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+static const struct pad_config gpio_table[] = {
+};
+
+const struct pad_config *__weak variant_base_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *__weak variant_override_gpio_table(size_t *num)
+{
+ *num = 0;
+ return NULL;
+}
+
+/* GPIOs needed prior to ramstage. */
+static const struct pad_config early_gpio_table[] = {
+};
+
+const struct pad_config *__weak
+variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000..c9f8b4c
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_GPIO_H
+#define BASEBOARD_GPIO_H
+
+#include <soc/gpio.h>
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000..18f90488
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef BASEBOARD_VARIANTS_H
+#define BASEBOARD_VARIANTS_H
+
+#include <soc/gpio.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* The next set of functions return the gpio table and fill in the number of
+ * entries for each table. */
+const struct pad_config *variant_base_gpio_table(size_t *num);
+const struct pad_config *variant_override_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_sleep_gpio_table(size_t *num, int slp_typ);
+
+/* Return memory SKU for the board. */
+size_t variant_memory_sku(void);
+
+/* Return ChromeOS gpio table and fill in number of entries. */
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+/* Modify devictree settings during ramstage. */
+struct device;
+void variant_update_devtree(struct device *dev);
+
+#endif /* BASEBOARD_VARIANTS_H */
diff --git a/src/mainboard/google/hatch/variants/hatch/Makefile.inc b/src/mainboard/google/hatch/variants/hatch/Makefile.inc
new file mode 100644
index 0000000..d4d8537
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/hatch/Makefile.inc
@@ -0,0 +1,17 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2018 Google LLC
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+ramstage-y += gpio.c
diff --git a/src/mainboard/google/hatch/variants/hatch/gpio.c b/src/mainboard/google/hatch/variants/hatch/gpio.c
new file mode 100644
index 0000000..24535f5
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/hatch/gpio.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+static const struct pad_config gpio_table[] = {
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+};
+
+const struct pad_config *variant_base_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h b/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h
new file mode 100644
index 0000000..c1622c6
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/hatch/include/variant/ec.h
@@ -0,0 +1,19 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_EC_H
+#define VARIANT_EC_H
+
+#endif
diff --git a/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h
new file mode 100644
index 0000000..49bb48c
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/hatch/include/variant/gpio.h
@@ -0,0 +1,21 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2018 Google LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+//#include <baseboard/gpio.h>
+
+#endif
diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
new file mode 100644
index 0000000..88df092
--- /dev/null
+++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb
@@ -0,0 +1,52 @@
+chip soc/intel/cannonlake
+ device domain 0 on
+ device pci 00.0 off end # Host Bridge
+ device pci 02.0 off end # Integrated Graphics Device
+ device pci 04.0 off end # SA Thermal device
+ device pci 12.0 off end # Thermal Subsystem
+ device pci 12.5 off end # UFS SCS
+ device pci 12.6 off end # GSPI #2
+ device pci 14.0 off end # USB xHCI
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 14.5 off end # SDCard
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 off end # SATA
+ device pci 19.0 off end # I2C #4
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1c.0 off end # PCI Express Port 1 (USB)
+ device pci 1c.1 off end # PCI Express Port 2 (USB)
+ device pci 1c.2 off end # PCI Express Port 3 (USB)
+ device pci 1c.3 off end # PCI Express Port 4 (USB)
+ device pci 1c.4 off end # PCI Express Port 5 (USB)
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 off end # PCI Express Port 13 (x4)
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 off end # LPC/eSPI
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 off end # Power Management Controller
+ device pci 1f.3 off end # Intel HDA
+ device pci 1f.4 off end # SMBus
+ device pci 1f.5 off end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5fc60c178f83034abe5d846d0f4169072b66f448
Gerrit-Change-Number: 30169
Gerrit-PatchSet: 1
Gerrit-Owner: Shelley Chen <shchen at google.com>
Gerrit-MessageType: newchange
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