[coreboot-gerrit] Change in ...coreboot[master]: Documentation/soc/intel/icelake: Fix references between documents

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30157


Change subject: Documentation/soc/intel/icelake: Fix references between documents
......................................................................

Documentation/soc/intel/icelake: Fix references between documents

Change-Id: Ifbdab15b1183998712f92d1f2f5340d2ad1451dc
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M Documentation/mainboard/google/dragonegg.md
M Documentation/mainboard/intel/icelake_rvp.md
M Documentation/soc/intel/icelake/iceLake_coreboot_development.md
3 files changed, 6 insertions(+), 6 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/30157/1

diff --git a/Documentation/mainboard/google/dragonegg.md b/Documentation/mainboard/google/dragonegg.md
index df4fe16..ef7e61b 100644
--- a/Documentation/mainboard/google/dragonegg.md
+++ b/Documentation/mainboard/google/dragonegg.md
@@ -4,14 +4,14 @@
 
 Dragonegg is based on Intel Ice Lake platform, please refer to below link to get more details
 ```eval_rst
-:doc:`../../soc/intel/iceLake_coreboot_development.md`
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
 ```
 
 ## Building coreboot
 
 * Follow build instructions mentioned in Ice Lake document
 ```eval_rst
-:doc:`../../soc/intel/iceLake_coreboot_development.md`
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
 ```
 
 * The default options for this board should result in a fully working image:
diff --git a/Documentation/mainboard/intel/icelake_rvp.md b/Documentation/mainboard/intel/icelake_rvp.md
index 09f2185..514ba6b 100644
--- a/Documentation/mainboard/intel/icelake_rvp.md
+++ b/Documentation/mainboard/intel/icelake_rvp.md
@@ -4,14 +4,14 @@
 
 Ice Lake RVP is based on Intel Ice Lake platform, please refer to below link to get more details
 ```eval_rst
-:doc:`../../soc/intel/iceLake_coreboot_development.md`
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
 ```
 
 ## Building coreboot
 
 * Follow build instructions mentioned in Ice Lake document
 ```eval_rst
-:doc:`../../soc/intel/iceLake_coreboot_development.md`
+:doc:`../../soc/intel/icelake/iceLake_coreboot_development`
 ```
 
 * The default options for this board should result in a fully working image:
diff --git a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md
index 6f194ca..5f8e279 100644
--- a/Documentation/soc/intel/icelake/iceLake_coreboot_development.md
+++ b/Documentation/soc/intel/icelake/iceLake_coreboot_development.md
@@ -17,12 +17,12 @@
 
 2. Additionally provides Firmware code support for Intel Reference Platform (RVP), known as Ice lake RVP with same SoC.
    ```eval_rst
-   :doc:`../../../mainboard/intel/icelake_rvp.md`
+   :doc:`../../../mainboard/intel/icelake_rvp`
    ```
 
 3. OEMs to design based on reference platform and make use of mainboard sample code. Dragonegg is Ice Lake based mainboard developed by Google
    ```eval_rst
-   :doc:`../../../mainboard/google/dragonegg.md`
+   :doc:`../../../mainboard/google/dragonegg`
    ```
 
 ### Summary:

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ifbdab15b1183998712f92d1f2f5340d2ad1451dc
Gerrit-Change-Number: 30157
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
Gerrit-MessageType: newchange
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