[coreboot-gerrit] Change in ...coreboot[master]: [WIP]mb/google/octopus: Override emmc DLL values for Phaser

[Bora Guvendik (Code Review)]

Bora Guvendik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30144


Change subject: [WIP]mb/google/octopus: Override emmc DLL values for Phaser
......................................................................

[WIP]mb/google/octopus: Override emmc DLL values for Phaser

New emmc DLL values for Phaser.

BUG=b:120561055
TEST=Boot to OS, chromeos-install, mmc_test

Change-Id: Ie8d56e0faf5c96d980c0614a61fbc6eacf582943
Signed-off-by: Bora Guvendik <bora.guvendik at intel.com>
---
M src/mainboard/google/octopus/variants/phaser/overridetree.cb
1 file changed, 41 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/30144/1

diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb
index f996d8b..a18dd7d 100644
--- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb
+++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb
@@ -1,5 +1,46 @@
 chip soc/intel/apollolake
 
+	# EMMC Tx CMD Delay
+	# Refer to EDS-Vol2-16.32.
+	# [14:8] steps of delay for DDR mode, each 125ps.
+	# [6:0] steps of delay for SDR mode, each 125ps.
+	register "emmc_tx_cmd_cntl" = "0x505"
+
+	# EMMC TX DATA Delay 1
+	# Refer to EDS-Vol2-16.33.
+	# [14:8] steps of delay for HS400, each 125ps.
+	# [6:0] steps of delay for SDR104/HS200, each 125ps.
+	register "emmc_tx_data_cntl1" = "0x0b0c"
+
+	# EMMC TX DATA Delay 2
+	# Refer to EDS-Vol2-16.34.
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_tx_data_cntl2" = "0x1c282929"
+
+	# EMMC RX CMD/DATA Delay 1
+	# Refer to EDS-Vol2-16.35.
+	# [30:24] steps of delay for SDR50, each 125ps.
+	# [22:16] steps of delay for DDR50, each 125ps.
+	# [14:8] steps of delay for SDR25/HS50, each 125ps.
+	# [6:0] steps of delay for SDR12, each 125ps.
+	register "emmc_rx_cmd_data_cntl1" = "0x00181b1b"
+
+	# EMMC RX CMD/DATA Delay 2
+	# Refer to EDS-Vol2-16.37.
+	# [17:16] stands for Rx Clock before Output Buffer
+	# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
+	# [6:0] steps of delay for HS200, each 125ps.
+	register "emmc_rx_cmd_data_cntl2" = "0x10028"
+
+	# EMMC Rx Strobe Delay
+	# Refer to EDS-Vol2-16.36.
+	# [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps.
+	# [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps.
+	register "emmc_rx_strobe_cntl" = "0x0b0b"
+
 	# Intel Common SoC Config
 	#+-------------------+---------------------------+
 	#| Field             |  Value                    |

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie8d56e0faf5c96d980c0614a61fbc6eacf582943
Gerrit-Change-Number: 30144
Gerrit-PatchSet: 1
Gerrit-Owner: Bora Guvendik <bora.guvendik at intel.com>
Gerrit-MessageType: newchange
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