[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Setup GPIOs again after FSP-S

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30113 )

Change subject: mb/google/sarien: Setup GPIOs again after FSP-S
......................................................................

mb/google/sarien: Setup GPIOs again after FSP-S

Currently CoffeeLake FSP is incorrectly modifying GPIO pad configuration
if specific UPD variables are not set as it expects.

This affects the display-related SOC pads with the following UPD variables:

UINT8 DdiPortBHpd; // GPP_E13
UINT8 DdiPortCHpd; // GPP_E14
UINT8 DdiPortDHpd; // GPP_E15
UINT8 DdiPortFHpd; // GPP_E16
UINT8 DdiPortBDdc; // GPP_E18/GPP_E19
UINT8 DdiPortCDdc; // GPP_E20/GPP_E21
UINT8 DdiPortDDdc; // GPP_E22/GPP_E23
UINT8 DdiPortFDdc; // GPP_H16/GPP_H17

Until FSP is fixed to not touch the pad configuration this workaround
will reprogram the GPIO settings after FSP-S step so they are correct
when the OS attempts to use them.

This was found in CoffeLake FSP Gold release:
https://github.com/IntelFsp/FSP/tree/master/CoffeeLakeFspBinPkg

As well as the current top-of-tree for the FSP sources.

BUG=b:120686247,chromium:913216
TEST=verify correct GPIO configuration for GPP_E group in the kernel

Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a
Signed-off-by: Duncan Laurie <dlaurie at google.com>
Reviewed-on: https://review.coreboot.org/c/30113
Tested-by: build bot (Jenkins) <no-reply at coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao at intel.com>
Reviewed-by: Furquan Shaikh <furquan at google.com>
---
M src/mainboard/google/sarien/ramstage.c
1 file changed, 11 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Lijian Zhao: Looks good to me, but someone else must approve



diff --git a/src/mainboard/google/sarien/ramstage.c b/src/mainboard/google/sarien/ramstage.c
index c65104b..c2dc27d 100644
--- a/src/mainboard/google/sarien/ramstage.c
+++ b/src/mainboard/google/sarien/ramstage.c
@@ -27,8 +27,19 @@
 	gpio_configure_pads(gpio_table, num_gpios);
 }
 
+/* Workaround FSP issue by reprogramming GPIOs after FSP-S */
+static void mainboard_init(struct device *dev)
+{
+	const struct pad_config *gpio_table;
+	size_t num_gpios;
+
+	gpio_table = variant_gpio_table(&num_gpios);
+	gpio_configure_pads(gpio_table, num_gpios);
+}
+
 static void mainboard_enable(struct device *dev)
 {
+	dev->ops->init = mainboard_init;
 	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I19550c4347cf65d409de6a8638619270372c4d0a
Gerrit-Change-Number: 30113
Gerrit-PatchSet: 3
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Duncan Laurie <dlaurie at chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan at google.com>
Gerrit-Reviewer: Lijian Zhao <lijian.zhao at intel.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi at google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Patrick Rudolph <siro at das-labor.org>
Gerrit-MessageType: merged
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