[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Fix I2C clock input

[Duncan Laurie (Code Review)]

Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30061


Change subject: soc/intel/cannonlake: Fix I2C clock input
......................................................................

soc/intel/cannonlake: Fix I2C clock input

The input clock for the I2C controllers was set at 133MHz but should
really be 216MHz according to the kernel:

https://patchwork.kernel.org/patch/10408729/
"Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C
than Sunrisepoint which uses 120 MHz. Preliminary information was that
both share the same clock rate but actual silicon implements elevated
rate for better support for 3.4 MHz high-speed I2C."

This change was tested on a sarien board where an I2C trackpad that was
measuring ~700MHz on I2C and is now measuring ~380MHz.

Change-Id: I792d1f013da5538a2b8157e2f99b754ca7b6bf70
Signed-off-by: Duncan Laurie <dlaurie at google.com>
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/30061/1

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 78c6dfe..9e007b6 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -197,7 +197,7 @@
 
 config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
 	int
-	default 133
+	default 216
 
 config SOC_INTEL_COMMON_BLOCK_GSPI_MAX
 	int

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I792d1f013da5538a2b8157e2f99b754ca7b6bf70
Gerrit-Change-Number: 30061
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie at chromium.org>
Gerrit-MessageType: newchange
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