[coreboot-gerrit] Change in ...coreboot[master]: mb/google/kahlee/variants/liara: Update eDP power off timing sequence

[chris wang (Code Review)]

Hello Chris Wang,

I'd like you to do a code review. Please visit

    https://review.coreboot.org/c/coreboot/+/30042

to review the following change.


Change subject: mb/google/kahlee/variants/liara: Update eDP power off timing sequence
......................................................................

mb/google/kahlee/variants/liara: Update eDP power off timing sequence

The eDP power off sequence doesn't meet panel spec.
To adjust the delay time from 20ms to 40ms.

BUG=b:118011567
TEST=emerge-grunt coreboot

Change-Id: I5540db34fa2d1fdea9326a2131c3ed50aacbaa9b
Signed-off-by: Chris Wang <chris.wang at amd.corp-partner.google.com>
---
M src/mainboard/google/kahlee/variants/liara/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/30042/1

diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb
index eef984a..41505fa 100644
--- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb
+++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb
@@ -21,7 +21,7 @@
 	register "uma_mode" = "UMAMODE_SPECIFIED_SIZE"
 	register "uma_size" = "32 * MiB"
 	register "lvds_poseq_varybl_to_blon" = "0x5" # in 4ms
-	register "lvds_poseq_blon_to_varybl" = "0x5" # in 4ms
+	register "lvds_poseq_blon_to_varybl" = "0xa" # in 4ms
 
 	# Enable I2C0 for audio, USB3 hub at 400kHz
 	register "i2c[0]" = "{

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5540db34fa2d1fdea9326a2131c3ed50aacbaa9b
Gerrit-Change-Number: 30042
Gerrit-PatchSet: 1
Gerrit-Owner: chris wang <Chris.Wang at amd.com>
Gerrit-Reviewer: Chris Wang <chris.wang at amd.corp-partner.google.com>
Gerrit-MessageType: newchange
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