[coreboot-gerrit] Change in ...coreboot[master]: riscv: fix non-SMP support

[Philipp Hug (Code Review)]

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29993


Change subject: riscv: fix non-SMP support
......................................................................

riscv: fix non-SMP support

Change an incorrect zero default of RISCV_HART_NUM to 1.
This causes causes a call to address 0.
Add a die() call to fail gracefully.

Change-Id: I4e3aa09b787ae0f26a4aae375f4e5fcd745a0a1e
Signed-off-by: Philipp Hug <philipp at hug.cx>
---
M src/arch/riscv/Kconfig
M src/arch/riscv/smp.c
2 files changed, 4 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29993/1

diff --git a/src/arch/riscv/Kconfig b/src/arch/riscv/Kconfig
index ae83be8..2d2ef5d 100644
--- a/src/arch/riscv/Kconfig
+++ b/src/arch/riscv/Kconfig
@@ -35,6 +35,7 @@
 
 config RISCV_HART_NUM
 	int
+	default 1
 
 config RISCV_WORKING_HARTID
 	int
diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c
index 8d07d39..b3feb9e 100644
--- a/src/arch/riscv/smp.c
+++ b/src/arch/riscv/smp.c
@@ -81,5 +81,8 @@
 		if (i != hartid)
 			set_msip(i, 1);
 
+	if (HLS()->entry.fn == NULL)
+		die("entry fn not set\n");
+
 	HLS()->entry.fn(HLS()->entry.arg);
 }

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I4e3aa09b787ae0f26a4aae375f4e5fcd745a0a1e
Gerrit-Change-Number: 29993
Gerrit-PatchSet: 1
Gerrit-Owner: Philipp Hug <philipp at hug.cx>
Gerrit-MessageType: newchange
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