[coreboot-gerrit] Change in coreboot[master]: riscv: add entry assembly file for RAMSTAGE

[Xiang Wang (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/28384

to look at the new patch set (#2).

Change subject: riscv: add entry assembly file for RAMSTAGE
......................................................................

riscv: add entry assembly file for RAMSTAGE

RAMSTAGE will revoke CAR/scratchpad, so stack and exception handling
needs to be moved to ddr memory. So add a assembly file to do this.

Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d
Signed-off-by: Xiang Wang <wxjstz at 126.com>
---
M src/arch/riscv/Makefile.inc
A src/arch/riscv/assembly_entry.S
M src/arch/riscv/include/arch/header.ld
3 files changed, 57 insertions(+), 0 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28384/2
-- 
To view, visit https://review.coreboot.org/28384
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I58aa6ff911f385180bad6e026d3c3eace846e37d
Gerrit-Change-Number: 28384
Gerrit-PatchSet: 2
Gerrit-Owner: Xiang Wang <wxjstz at 126.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180829/7dd7f513/attachment.html>