[coreboot-gerrit] Change in coreboot[master]: Documentation/nb/intel/sandybridge/nri_registers.md: Fix mistake
Angel Pons (Code Review)
gerrit at coreboot.org
Tue Aug 28 20:41:13 CEST 2018
Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28377
Change subject: Documentation/nb/intel/sandybridge/nri_registers.md: Fix mistake
......................................................................
Documentation/nb/intel/sandybridge/nri_registers.md: Fix mistake
According to a comment on fa1a07b, the 100MHz clock is the Ivy Bridge
only clock, not the 133MHz one.
Change-Id: I28fed4a9264b96f93b9e88325f547a5db512514c
Signed-off-by: Angel Pons <th3fanbus at gmail.com>
---
M Documentation/northbridge/intel/sandybridge/nri_registers.md
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28377/1
diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md
index d5857ec..aa16644 100644
--- a/Documentation/northbridge/intel/sandybridge/nri_registers.md
+++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md
@@ -2137,8 +2137,8 @@
+===========+==================================================================+
| 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] |
+-----------+------------------------------------------------------------------+
-| 8 | - 1: 100Mhz reference clock |
-| | - 0: 133Mhz reference clock (Ivy Bridge only) |
+| 8 | - 1: 100Mhz reference clock (Ivy Bridge only) |
+| | - 0: 133Mhz reference clock |
+-----------+------------------------------------------------------------------+
| 31 | PLL busy |
+-----------+------------------------------------------------------------------+
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I28fed4a9264b96f93b9e88325f547a5db512514c
Gerrit-Change-Number: 28377
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <th3fanbus at gmail.com>
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