[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
Richard Spiegel (Code Review)
gerrit at coreboot.org
Sat Aug 25 01:37:06 CEST 2018
Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/28341
Change subject: soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
......................................................................
soc/amd/stoneyridge/enable_usbdebug.c: Update pci_ehci_dbg_set_port()
Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL,
which was deprecated in favor of a public PCI register (though only the
bits to enable debug port became public) 0x90. Therefor code needs to be
updated.
BUG=b:69231009
TEST=Build and boot grunt.
Change-Id: I47b0e4450f96399fc3066d0a974e7a9324d82f90
Signed-off-by: Richard Spiegel <richard.spiegel at silverbackltd.com>
---
M src/soc/amd/stoneyridge/include/soc/southbridge.h
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/28341/1
diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h
index f054b3b..5f1faea 100644
--- a/src/soc/amd/stoneyridge/include/soc/southbridge.h
+++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h
@@ -308,7 +308,7 @@
#define EHCI_HUB_CONFIG4 0x90
#define DEBUG_PORT_SELECT_SHIFT 16
#define DEBUG_PORT_ENABLE BIT(18)
-#define DEBUG_PORT_MASK (BIT(16) | BIT(17) | (BIT(18))
+#define DEBUG_PORT_MASK ( BIT(16) | BIT(17) | (BIT(18) )
#define WIDEIO_RANGE_ERROR -1
#define TOTAL_WIDEIO_PORTS 3
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I47b0e4450f96399fc3066d0a974e7a9324d82f90
Gerrit-Change-Number: 28341
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Spiegel <richard.spiegel at silverbackltd.com>
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