[coreboot-gerrit] Change in coreboot[master]: mb/google/poppy/variant/nami: Tune Fan speed

[TH Lin (Code Review)]

TH Lin has uploaded this change for review. ( https://review.coreboot.org/28186


Change subject: mb/google/poppy/variant/nami: Tune Fan speed
......................................................................

mb/google/poppy/variant/nami: Tune Fan speed

Rescale DFPS table from 10% Level to 5% level

BUG=b:112438998#3
BRANCH=nami
TEST=emerge-nami coreboot chromeos-bootimage
Test image with dptf.dv

Change-Id: I680ee589872e998ba69735cb03728e2d83f187cc
Signed-off-by: T.H. Lin <t.h_lin at quanta.corp-partner.google.com>
---
M src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
1 file changed, 37 insertions(+), 6 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/28186/1

diff --git a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
index 03567fc..caf3689 100644
--- a/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/nami/include/variant/acpi/dptf.asl
@@ -41,6 +41,16 @@
 #define DPTF_TSR1_ACTIVE_AC3    42
 #define DPTF_TSR1_ACTIVE_AC4    39
 
+#define DPTF_TSR2_SENSOR_ID	2
+#define DPTF_TSR2_SENSOR_NAME	"Thermal_Sensor_Remote_CPU"
+#define DPTF_TSR2_PASSIVE	75
+#define DPTF_TSR2_CRITICAL	125
+#define DPTF_TSR2_ACTIVE_AC0	50
+#define DPTF_TSR2_ACTIVE_AC1	47
+#define DPTF_TSR2_ACTIVE_AC2	45
+#define DPTF_TSR2_ACTIVE_AC3	42
+#define DPTF_TSR2_ACTIVE_AC4	39
+
 #define DPTF_ENABLE_CHARGER
 #define DPTF_ENABLE_FAN_CONTROL
 
@@ -61,12 +71,26 @@
 	 *	  These are initial reference values.
 	 */
 	/* Control, Trip Point, Speed, NoiseLevel, Power */
-	Package () {90,		0xFFFFFFFF,	6700,	220,	2200},
-	Package () {69,		0xFFFFFFFF,	5800,	180,	1800},
-	Package () {56,		0xFFFFFFFF,	5000,	145,	1450},
-	Package () {46,		0xFFFFFFFF,	4900,	115,	1150},
-	Package () {36,		0xFFFFFFFF,	3900,	90,	900},
-	Package () { 0,         0xFFFFFFFF,        0,    0,       0}
+	Package () {100,	0xFFFFFFFF,	6700,	250,	2500},
+	Package () {90,		0xFFFFFFFF,	6300,	225,	2250},
+	Package () {85,		0xFFFFFFFF,	6000,	210,	2100},
+	Package () {80,		0xFFFFFFFF,	5800,	200,	2000},
+	Package () {75,		0xFFFFFFFF,	5400,	185,	1850},
+	Package () {70,		0xFFFFFFFF,	5000,	175,	1750},
+	Package () {65,		0xFFFFFFFF,	4700,	160,	1600},
+	Package () {60,		0xFFFFFFFF,	4400,	150,	1500},
+	Package () {55,		0xFFFFFFFF,	4100,	135,	1350},
+	Package () {50,		0xFFFFFFFF,	3800,	125,	1250},
+	Package () {45,		0xFFFFFFFF,	3500,	110,	1100},
+	Package () {40,		0xFFFFFFFF,	3300,	100,	1000},
+	Package () {35,		0xFFFFFFFF,	2900,	85,	800},
+	Package () {30,		0xFFFFFFFF,	2500,	75,	750},
+	Package () {25,		0xFFFFFFFF,	2000,	60,	600},
+	Package () {20,		0xFFFFFFFF,	1500,	50,	500},
+	Package () {15,		0xFFFFFFFF,	1000,	35,	350},
+	Package () {10,		0xFFFFFFFF,	800,	25,	250},
+	Package () {5,		0xFFFFFFFF,	500,	10,	150},
+	Package () {0,		0xFFFFFFFF,	0,	0,	50}
 })
 
 Name (DART, Package () {
@@ -87,6 +111,10 @@
 	Package () {
 		\_SB.DPTF.TFN1, \_SB.DPTF.TSR1, 100, 90, 69, 56, 46, 36, 0, 0,
 			0, 0, 0
+	},
+	Package () {
+		\_SB.DPTF.TFN1, \_SB.DPTF.TSR2, 100, 90, 69, 56, 46, 36, 0, 0,
+			0, 0, 0
 	}
 })
 #endif
@@ -100,6 +128,9 @@
 
 	/* CPU Throttle Effect on TSR1 */
 	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 1, 0, 0, 0, 0 },
+
+	/* CPU Throttle Effect on TSR2 */
+	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 1, 0, 0, 0, 0 },
 })
 
 Name (MPPC, Package ()

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I680ee589872e998ba69735cb03728e2d83f187cc
Gerrit-Change-Number: 28186
Gerrit-PatchSet: 1
Gerrit-Owner: TH Lin <t.h_lin at quanta.corp-partner.google.com>
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