[coreboot-gerrit] Change in coreboot[master]: eve: move DPTF DTRT table to the root scope

[Lucas Chen (Code Review)]

Lucas Chen has uploaded this change for review. ( https://review.coreboot.org/28077


Change subject: eve: move DPTF DTRT table to the root scope
......................................................................

eve: move DPTF DTRT table to the root scope

Non-cros DPTF policies require absolute name references in the _TRT
method. However, coreboot compiles ASL code with name reference
optimization enabled, which turns absolute name references to
relative name references. That said, the \_SB prefix of the entries
in DTRT will be removed. For example, \_SB.PCI0.B0D4 in DTRT will
be optimized to PCI0.B0D4 since DTRT is under the \_SB scope.

In order to keep the absolute name ref, the DTRT table is moved to
the root scope.

BRANCH=eve
BUG=b:73133864
TEST=Install DPTF UI and check the nodes in passive policy are valid

Change-Id: I6a4a5fd5da3a639c611bd4cb45d2cf6e9cba9397
Signed-off-by: Lucas Chen <lucas.chen at quanta.corp-partner.google.com>
---
M src/mainboard/google/eve/acpi/dptf.asl
M src/soc/intel/skylake/acpi/dptf/dptf.asl
2 files changed, 19 insertions(+), 17 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28077/1

diff --git a/src/mainboard/google/eve/acpi/dptf.asl b/src/mainboard/google/eve/acpi/dptf.asl
index 7dd4249..3d840b4 100644
--- a/src/mainboard/google/eve/acpi/dptf.asl
+++ b/src/mainboard/google/eve/acpi/dptf.asl
@@ -48,28 +48,30 @@
 	Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 },	/* 500mA */
 })
 
-Name (DTRT, Package () {
-	/* CPU Throttle Effect on CPU */
-	Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 10, 0, 0, 0, 0 },
+Scope(\) {
+	Name (DTRT, Package () {
+		/* CPU Throttle Effect on CPU */
+		Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 },
 
-	/* CPU Effect on Ambient */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+		/* CPU Effect on Ambient */
+		Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
 
-	/* CPU Effect on Charger */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 50, 600, 0, 0, 0, 0 },
+		/* CPU Effect on Charger */
+		Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 50, 600, 0, 0, 0, 0 },
 
-	/* CPU Effect on DRAM */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+		/* CPU Effect on DRAM */
+		Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
 
-	/* CPU Effect on eMMC */
-	Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 50, 600, 0, 0, 0, 0 },
+		/* CPU Effect on eMMC */
+		Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 50, 600, 0, 0, 0, 0 },
 
-	/* Charger Throttle Effect on Charger (TSR1) */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+		/* Charger Throttle Effect on Charger (TSR1) */
+		Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
 
-	/* Charger Throttle Effect on eMMC (TSR3) */
-	Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
-})
+		/* Charger Throttle Effect on eMMC (TSR3) */
+		Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 },
+	})
+}
 
 Name (MPPC, Package ()
 {
diff --git a/src/soc/intel/skylake/acpi/dptf/dptf.asl b/src/soc/intel/skylake/acpi/dptf/dptf.asl
index 61f982c..98e302c 100644
--- a/src/soc/intel/skylake/acpi/dptf/dptf.asl
+++ b/src/soc/intel/skylake/acpi/dptf/dptf.asl
@@ -73,7 +73,7 @@
 
 	Method (_TRT)
 	{
-		Return (\_SB.DTRT)
+                Return (\DTRT)
 	}
 
 #ifdef DPTF_ENABLE_FAN_CONTROL

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I6a4a5fd5da3a639c611bd4cb45d2cf6e9cba9397
Gerrit-Change-Number: 28077
Gerrit-PatchSet: 1
Gerrit-Owner: Lucas Chen <lucas.chen at quanta.corp-partner.google.com>
Gerrit-Reviewer: Wei Shun Chang <wei.shun.chang at intel.com>
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