[coreboot-gerrit] Change in coreboot[master]: minnowmax: allow both 1333 and 1066 MHz memory SKUs

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27989 )

Change subject: minnowmax: allow both 1333 and 1066 MHz memory SKUs
......................................................................


Patch Set 2:

(8 comments)

https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romstage.c
File src/mainboard/intel/minnowmax/romstage.c:

https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romstage.c@61
PS2, Line 61: 	.DRAMType = 1,       /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/
line over 80 characters


https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romstage.c@65
PS2, Line 65: 	.DIMMDensity = 1,    /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */
line over 80 characters


https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romstage.c@66
PS2, Line 66: 	.DIMMBusWidth = 3,   /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */
line over 80 characters


https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romstage.c@69
PS2, Line 69: 	.DIMMtRPtRCD = 11,    /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
line over 80 characters


https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romstage.c@80
PS2, Line 80: 	.DRAMType = 1,       /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/
line over 80 characters


https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romstage.c@84
PS2, Line 84: 	.DIMMDensity = 1,    /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */
line over 80 characters


https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romstage.c@85
PS2, Line 85: 	.DIMMBusWidth = 3,   /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */
line over 80 characters


https://review.coreboot.org/#/c/27989/2/src/mainboard/intel/minnowmax/romstage.c@88
PS2, Line 88: 	.DIMMtRPtRCD = 9,    /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
line over 80 characters



-- 
To view, visit https://review.coreboot.org/27989
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I5e57dd419b443dfa742c8812cec87274af557728
Gerrit-Change-Number: 27989
Gerrit-PatchSet: 2
Gerrit-Owner: Michał Żygowski <michal.zygowski at 3mdeb.com>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski at 3mdeb.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Thu, 09 Aug 2018 21:30:32 +0000
Gerrit-HasComments: Yes
Gerrit-HasLabels: No
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180809/51db2ab7/attachment.html>