[coreboot-gerrit] Change in coreboot[master]: minnowmax: allow both 1333 and 1066 MHz memory SKUs

build bot (Jenkins) (Code Review) gerrit at coreboot.org
Thu Aug 9 19:22:15 CEST 2018


build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27989 )

Change subject: minnowmax: allow both 1333 and 1066 MHz memory SKUs
......................................................................


Patch Set 1:

(8 comments)

https://review.coreboot.org/#/c/27989/1/src/mainboard/intel/minnowmax/romstage.c
File src/mainboard/intel/minnowmax/romstage.c:

https://review.coreboot.org/#/c/27989/1/src/mainboard/intel/minnowmax/romstage.c@60
PS1, Line 60: 	.DRAMType = 1,       /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/
line over 80 characters


https://review.coreboot.org/#/c/27989/1/src/mainboard/intel/minnowmax/romstage.c@64
PS1, Line 64: 	.DIMMDensity = 1,    /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */
line over 80 characters


https://review.coreboot.org/#/c/27989/1/src/mainboard/intel/minnowmax/romstage.c@65
PS1, Line 65: 	.DIMMBusWidth = 3,   /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */
line over 80 characters


https://review.coreboot.org/#/c/27989/1/src/mainboard/intel/minnowmax/romstage.c@68
PS1, Line 68: 	.DIMMtRPtRCD = 11,    /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
line over 80 characters


https://review.coreboot.org/#/c/27989/1/src/mainboard/intel/minnowmax/romstage.c@79
PS1, Line 79: 	.DRAMType = 1,       /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/
line over 80 characters


https://review.coreboot.org/#/c/27989/1/src/mainboard/intel/minnowmax/romstage.c@83
PS1, Line 83: 	.DIMMDensity = 1,    /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */
line over 80 characters


https://review.coreboot.org/#/c/27989/1/src/mainboard/intel/minnowmax/romstage.c@84
PS1, Line 84: 	.DIMMBusWidth = 3,   /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */
line over 80 characters


https://review.coreboot.org/#/c/27989/1/src/mainboard/intel/minnowmax/romstage.c@87
PS1, Line 87: 	.DIMMtRPtRCD = 9,    /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
line over 80 characters



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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: comment
Gerrit-Change-Id: I5e57dd419b443dfa742c8812cec87274af557728
Gerrit-Change-Number: 27989
Gerrit-PatchSet: 1
Gerrit-Owner: Michał Żygowski <michal.zygowski at 3mdeb.com>
Gerrit-CC: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-Comment-Date: Thu, 09 Aug 2018 17:22:15 +0000
Gerrit-HasComments: Yes
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