[coreboot-gerrit] Change in coreboot[master]: mb/google/octopus/variants/fleex: Setup DPTF table
John Su (Code Review)
gerrit at coreboot.org
Thu Aug 9 08:34:11 CEST 2018
John Su has uploaded this change for review. ( https://review.coreboot.org/27969
Change subject: mb/google/octopus/variants/fleex: Setup DPTF table
......................................................................
mb/google/octopus/variants/fleex: Setup DPTF table
Follow thermal table for first tunning.
BUG=b:112274477
TEST=Match the result from DPTF UI.
Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244
Signed-off-by: John Su <john_su at compal.corp-partner.google.com>
---
M src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl
1 file changed, 71 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/27969/1
diff --git a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl
index cc17d56..bbcdc70 100644
--- a/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/octopus/variants/fleex/include/variant/acpi/dptf.asl
@@ -13,4 +13,74 @@
* GNU General Public License for more details.
*/
-#include <baseboard/acpi/dptf.asl>
+#define DPTF_CPU_PASSIVE 90
+#define DPTF_CPU_CRITICAL 127
+#define DPTF_CPU_ACTIVE_AC0 87
+#define DPTF_CPU_ACTIVE_AC1 85
+#define DPTF_CPU_ACTIVE_AC2 83
+#define DPTF_CPU_ACTIVE_AC3 80
+#define DPTF_CPU_ACTIVE_AC4 75
+
+#define DPTF_TSR0_SENSOR_ID 0
+#define DPTF_TSR0_SENSOR_NAME "Battery"
+#define DPTF_TSR0_PASSIVE 90
+#define DPTF_TSR0_CRITICAL 127
+
+#define DPTF_TSR1_SENSOR_ID 1
+#define DPTF_TSR1_SENSOR_NAME "Ambient"
+#define DPTF_TSR1_PASSIVE 90
+#define DPTF_TSR1_CRITICAL 127
+
+#define DPTF_TSR2_SENSOR_ID 2
+#define DPTF_TSR2_SENSOR_NAME "Charger"
+#define DPTF_TSR2_PASSIVE 90
+#define DPTF_TSR2_CRITICAL 127
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */
+})
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 500, 10, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 500, 10, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 2 */
+ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 500, 10, 0, 0, 0, 0 },
+#endif
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, /* Revision */
+ Package () { /* Power Limit 1 */
+ 0, /* PowerLimitIndex, 0 for Power Limit 1 */
+ 3000, /* PowerLimitMinimum */
+ 4500, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 500 /* StepSize */
+ },
+
+ Package () { /* Power Limit 2 */
+ 1, /* PowerLimitIndex, 1 for Power Limit 2 */
+ 15000, /* PowerLimitMinimum */
+ 15000, /* PowerLimitMaximum */
+ 1000, /* TimeWindowMinimum */
+ 1000, /* TimeWindowMaximum */
+ 500 /* StepSize */
+ }
+})
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244
Gerrit-Change-Number: 27969
Gerrit-PatchSet: 1
Gerrit-Owner: John Su <john_su at compal.corp-partner.google.com>
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