[coreboot-gerrit] Change in coreboot[master]: arm64: Remove set_cntfrq() function

[Julius Werner (Code Review)]

Julius Werner has uploaded this change for review. ( https://review.coreboot.org/27947


Change subject: arm64: Remove set_cntfrq() function
......................................................................

arm64: Remove set_cntfrq() function

CNTFRQ_EL0 is a normal AArch64 architectural register like hundreds of
others that are all accessed through the raw_(read|write)_${register}()
family of functions. There's no reason why this register in particular
should have an inconsistent accessor, so replace all instances of
set_cntfrq() with raw_write_cntfrq_el0() and get rid of it.

Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b
Signed-off-by: Julius Werner <jwerner at chromium.org>
---
M src/arch/arm64/armv8/lib/Makefile.inc
D src/arch/arm64/armv8/lib/clock.c
D src/arch/arm64/include/arch/clock.h
M src/soc/cavium/cn81xx/timer.c
M src/soc/nvidia/tegra210/ramstage.c
5 files changed, 5 insertions(+), 55 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/27947/1

diff --git a/src/arch/arm64/armv8/lib/Makefile.inc b/src/arch/arm64/armv8/lib/Makefile.inc
index bfc87c3..8fc44de 100644
--- a/src/arch/arm64/armv8/lib/Makefile.inc
+++ b/src/arch/arm64/armv8/lib/Makefile.inc
@@ -15,7 +15,7 @@
 ##
 ################################################################################
 
-lib_access = pstate.c sysctrl.c cache.c tlb.c clock.c
+lib_access = pstate.c sysctrl.c cache.c tlb.c
 
 ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y)
 decompressor-y += $(lib_access)
diff --git a/src/arch/arm64/armv8/lib/clock.c b/src/arch/arm64/armv8/lib/clock.c
deleted file mode 100644
index f15adf4..0000000
--- a/src/arch/arm64/armv8/lib/clock.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * clock.c: Functions for accessing clock and timer related registers
- * Reference: ARM Architecture Reference Manual, ARMv8-A edition
- */
-
-#include <stdint.h>
-
-#include <arch/clock.h>
-
-void set_cntfrq(uint32_t freq)
-{
-	__asm__ __volatile__("msr cntfrq_el0, %0" :: "r"((uint64_t)freq));
-}
diff --git a/src/arch/arm64/include/arch/clock.h b/src/arch/arm64/include/arch/clock.h
deleted file mode 100644
index 77d09d8..0000000
--- a/src/arch/arm64/include/arch/clock.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ARM_CLOCK_H_
-#define __ARM_CLOCK_H_
-
-#include <types.h>
-
-void set_cntfrq(uint32_t);
-
-#endif /* __ARM_CLOCK_H_ */
diff --git a/src/soc/cavium/cn81xx/timer.c b/src/soc/cavium/cn81xx/timer.c
index b1c2285..f2a870a 100644
--- a/src/soc/cavium/cn81xx/timer.c
+++ b/src/soc/cavium/cn81xx/timer.c
@@ -17,6 +17,7 @@
  */
 
 #include <arch/io.h>
+#include <arch/lib_helpers.h>
 #include <console/console.h>
 #include <inttypes.h>
 #include <soc/clock.h>
@@ -25,7 +26,6 @@
 #include <timer.h>
 #include <soc/addressmap.h>
 #include <assert.h>
-#include <arch/clock.h>
 
 /* Global System Timers Unit (GTI) registers */
 struct cn81xx_timer {
@@ -131,7 +131,7 @@
 
 void soc_timer_init(void)
 {
-	set_cntfrq(tickrate);
+	raw_write_cntfrq_el0(tickrate);
 }
 
 /**
diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c
index 18fdded..86fae67 100644
--- a/src/soc/nvidia/tegra210/ramstage.c
+++ b/src/soc/nvidia/tegra210/ramstage.c
@@ -13,8 +13,8 @@
  * GNU General Public License for more details.
  */
 
-#include <arch/clock.h>
 #include <arch/cpu.h>
+#include <arch/lib_helpers.h>
 #include <arch/stages.h>
 #include <gic.h>
 #include <soc/addressmap.h>
@@ -26,7 +26,7 @@
 {
 	uint32_t freq = clock_get_osc_khz() * 1000;
 	// Set the cntfrq register.
-	set_cntfrq(freq);
+	raw_write_cntfrq_el0(freq);
 }
 
 static void mselect_enable_wrap(void)

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I599519ba71c287d4085f9ad28d7349ef0b1eea9b
Gerrit-Change-Number: 27947
Gerrit-PatchSet: 1
Gerrit-Owner: Julius Werner <jwerner at chromium.org>
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