[coreboot-gerrit] Change in coreboot[master]: nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware

[Arthur Heymans (Code Review)]

Hello build bot (Jenkins), 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/27873

to look at the new patch set (#3).

Change subject: nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware
......................................................................

nb/intel/*: Use 2M TSEG instead of 8M on pre-arrandale hardware

8M was set in the assumption that at least 4M was needed for IED
(Intel Enhanced Debug) , but this is not true.

The SMRR MTRR's need to have TSEG aligned to its size which is easier when TSEG
is only 2M. Also at most 6M of RAM more becomes available for use.

Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/gm45/raminit.c
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/pineview/raminit.c
M src/northbridge/intel/x4x/raminit_ddr23.c
4 files changed, 16 insertions(+), 10 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/27873/3
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I4b114c8dc13699b3c034f0a7060181d9d590737b
Gerrit-Change-Number: 27873
Gerrit-PatchSet: 3
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
Gerrit-Reviewer: build bot (Jenkins) <no-reply at coreboot.org>
Gerrit-CC: Patrick Rudolph <siro at das-labor.org>
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