[coreboot-gerrit] Change in coreboot[master]: mb/google/fizz: Tune DPTF settings

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/25924


Change subject: mb/google/fizz: Tune DPTF settings
......................................................................

mb/google/fizz: Tune DPTF settings

This patch reduces tcc_offset value from 6 to 0. Also, set the
CPU critical temperature threshold to 105 degree celcius from 100.
These are the fine tuned values to avoid the over heating condition.

Change-Id: Ia0e4e054e68a9059f38934ec0d39cb5c2c24f043
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar at intel.com>
---
M src/mainboard/google/fizz/acpi/dptf.asl
M src/mainboard/google/fizz/devicetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/25924/1

diff --git a/src/mainboard/google/fizz/acpi/dptf.asl b/src/mainboard/google/fizz/acpi/dptf.asl
index f877c71..fb7cf91 100644
--- a/src/mainboard/google/fizz/acpi/dptf.asl
+++ b/src/mainboard/google/fizz/acpi/dptf.asl
@@ -15,7 +15,7 @@
  */
 
 #define DPTF_CPU_PASSIVE	93
-#define DPTF_CPU_CRITICAL	100
+#define DPTF_CPU_CRITICAL	105
 #define DPTF_CPU_ACTIVE_AC0	90
 #define DPTF_CPU_ACTIVE_AC1	77
 
diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb
index 9d120ea..1f11060 100644
--- a/src/mainboard/google/fizz/devicetree.cb
+++ b/src/mainboard/google/fizz/devicetree.cb
@@ -312,7 +312,7 @@
 	register "speed_shift_enable" = "1"
 	register "tdp_psyspl2" = "90"
 	register "psys_pmax" = "120"
-	register "tcc_offset" = "6"     # TCC of 94C
+	register "tcc_offset" = "0"     # TCC of 100C
 
 	# Use default SD card detect GPIO configuration
 	register "sdcard_cd_gpio_default" = "GPP_A7"

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Ia0e4e054e68a9059f38934ec0d39cb5c2c24f043
Gerrit-Change-Number: 25924
Gerrit-PatchSet: 1
Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar at intel.com>
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