[coreboot-gerrit] Change in coreboot[master]: fsp2_0/cannonlake: Add MP services UPDs into FSP-S header
Subrata Banik (Code Review)
gerrit at coreboot.org
Mon Apr 30 11:46:51 CEST 2018
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/25922
Change subject: fsp2_0/cannonlake: Add MP services UPDs into FSP-S header
......................................................................
fsp2_0/cannonlake: Add MP services UPDs into FSP-S header
Add 2 FSP-S UPD to make use of coreboot MP service PPI structure
* CpuMpPpi - Pointer to MP service PPI
* CpuInitMpLibHob - Pointer for CPU data Hob [N/A for coreboot]
BRANCH=none
BUG=b:74436746
TEST=None
Change-Id: I7eddc650c78777504768e7820ec04742908ac77a
Signed-off-by: Subrata Banik <subrata.banik at intel.com>
---
M src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
1 file changed, 22 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/25922/1
diff --git a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
index 4daf891..14fa8cd 100644
--- a/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
+++ b/src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspsUpd.h
@@ -1093,22 +1093,25 @@
**/
UINT16 ImonSlope1[5];
-/** Offset 0x0324 - CPU VR Power Delivery Design
- Used to communicate the power delivery design capability of the board. This value
- is an enum of the available power delivery segments that are defined in the Platform
- Design Guide.
+/** Offset 0x0324 - CpuMpPpi
+ Pointer for CpuMpPpi
**/
- UINT32 VrPowerDeliveryDesign;
+ UINT32 CpuMpPpi;
-/** Offset 0x0328 - ReservedCpuPostMemProduction
+/** Offset 0x0328 - CpuInitMpLibHob
+ Pointer for CpuInitMpLibHob
+**/
+ UINT32 CpuInitMpLibHob;
+
+/** Offset 0x032C - ReservedCpuPostMemProduction
Reserved for CPU Post-Mem Production
$EN_DIS
**/
UINT8 ReservedCpuPostMemProduction[1];
-/** Offset 0x0329
+/** Offset 0x032D
**/
- UINT8 UnusedUpdSpace10[29];
+ UINT8 UnusedUpdSpace10[25];
/** Offset 0x0346 - Enable DMI ASPM
Deprecated.
@@ -1876,6 +1879,7 @@
0x19: 20kOhm weak pull-up - Enable/disable SerialIo I2C0,I2C1,I2C2,I2C3,I2C4,I2C5
pads termination respectively. One byte for each controller, byte0 for I2C0, byte1
for I2C1, and so on.
+ 0x1:None, 0x13:1kOhm WPU, 0x15:5kOhm WPU, 0x19:20kOhm WPU
**/
UINT8 PchSerialIoI2cPadsTermination[6];
@@ -2154,17 +2158,9 @@
**/
UINT8 SataRstCpuAttachedStorage;
-/** Offset 0x0752 - Enable 8254 Static Clock Gating On S3
- This is only applicable when Enable8254ClockGating is disabled. FSP will do the
- 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
- avoids the SMI requirement for the programming.
- $EN_DIS
+/** Offset 0x0752
**/
- UINT8 Enable8254ClockGatingOnS3;
-
-/** Offset 0x0753
-**/
- UINT8 UnusedUpdSpace25;
+ UINT8 UnusedUpdSpace25[2];
/** Offset 0x0754 - Pch PCIE device override table pointer
The PCIe device table is being used to override PCIe device ASPM settings. This
@@ -2297,7 +2293,7 @@
**/
UINT8 ChapDeviceEnable;
-/** Offset 0x07B2 - Skip PAM register lock
+/** Offset 0x07B2 - Skip PAM regsiter lock
Enable: PAM register will not be locked by RC, platform code should lock it, Disable(Default):
PAM registers will be locked by RC
$EN_DIS
@@ -2480,7 +2476,7 @@
/** Offset 0x07DA - Tcc Offset Lock
Tcc Offset Lock for Runtime Average Temperature Limit (RATL) to lock temperature
- target; <b>0: Disabled</b>; 1: Enabled.
+ target; 0: Disabled; <b>1: Enabled </b>.
$EN_DIS
**/
UINT8 TccOffsetLock;
@@ -2844,10 +2840,9 @@
**/
UINT16 PsysPmax;
-/** Offset 0x0858 - Interrupt Response Time Limit of C-State LatencyContol0
- Interrupt Response Time Limit of C-State LatencyContol0.Range of value 0 to 0x3FF
+/** Offset 0x0858
**/
- UINT16 CstateLatencyControl0Irtl;
+ UINT8 Reserved0[2];
/** Offset 0x085A - Interrupt Response Time Limit of C-State LatencyContol1
Interrupt Response Time Limit of C-State LatencyContol1.Range of value 0 to 0x3FF
@@ -2894,13 +2889,13 @@
/** Offset 0x0870 - Package PL4 power limit
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 1023875 in Step size of 125
+ Range 0 to 4095875 in Step size of 125
**/
UINT32 PowerLimit4;
/** Offset 0x0874 - Tcc Offset Time Window for RATL
Package PL4 power limit. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.Valid
- Range 0 to 1023875 in Step size of 125
+ Range 0 to 4095875 in Step size of 125
**/
UINT32 TccOffsetTimeWindowForRatl;
@@ -3089,7 +3084,8 @@
UINT8 PchUnlockGpioPads;
/** Offset 0x08C2 - PCH Unlock SBI access
- Deprecated
+ This unlock the SBI lock bit to allow SBI after post time. 0: Lock SBI access; 1:
+ Unlock SBI access.
$EN_DIS
**/
UINT8 PchSbiUnlock;
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I7eddc650c78777504768e7820ec04742908ac77a
Gerrit-Change-Number: 25922
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik at intel.com>
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