[coreboot-gerrit] Change in coreboot[master]: arch/x86: Relocating GDT in romstage

[Hannah Williams (Code Review)]

Hannah Williams has uploaded this change for review. ( https://review.coreboot.org/25895


Change subject: arch/x86: Relocating GDT in romstage
......................................................................

arch/x86: Relocating GDT in romstage

While in Cache as RAM, move the GDT from Flash to CAR

Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a
Signed-off-by: Hannah Williams <hannah.williams at intel.com>
---
M src/arch/x86/Makefile.inc
M src/arch/x86/assembly_entry.S
A src/arch/x86/gdt_init.S
3 files changed, 48 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/25895/1

diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 07bef93..f45295c 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -206,6 +206,7 @@
 
 romstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c
 romstage-y += boot.c
+romstage-y += gdt_init.S
 romstage-y += cbmem.c
 romstage-y += cbfs_and_run.c
 romstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += cpu_common.c
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S
index e5e7d48..5a8a57e 100644
--- a/src/arch/x86/assembly_entry.S
+++ b/src/arch/x86/assembly_entry.S
@@ -64,6 +64,9 @@
 #endif
 
 	andl	$0xfffffff0, %esp
+#if ENV_ROMSTAGE
+	call    _gdt_init
+#endif
 #if IS_ENABLED(CONFIG_IDT_IN_EVERY_STAGE)
 	call	exception_init
 #endif
diff --git a/src/arch/x86/gdt_init.S b/src/arch/x86/gdt_init.S
new file mode 100644
index 0000000..bfc5e45
--- /dev/null
+++ b/src/arch/x86/gdt_init.S
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+	.code32
+	.globl _gdt_init
+_gdt_init:
+	cli
+	lgdt	%cs:gdtptr
+	ret
+
+	.text
+	.align	4
+.globl gdtptr
+gdt:
+gdtptr:
+	.word	gdt_end - gdt -1 /* compute the table limit */
+	.long	gdt		 /* we know the offset */
+	.word	0
+
+	/* selgdt 0x08, flat code segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes
+					  for limit */
+
+	/* selgdt 0x10,flat data segment */
+	.word	0xffff, 0x0000
+	.byte	0x00, 0x93, 0xcf, 0x00
+
+	/* selgdt 0x18, flat code segment (64-bit) */
+	.word   0xffff, 0x0000
+	.byte   0x00, 0x9b, 0xaf, 0x00
+
+gdt_end:
+
+.code32

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a
Gerrit-Change-Number: 25895
Gerrit-PatchSet: 1
Gerrit-Owner: Hannah Williams <hannah.williams at intel.com>
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