[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Use common i2c function instead of soc
Maulik V Vaghela (Code Review)
gerrit at coreboot.org
Tue Apr 24 10:53:21 CEST 2018
Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/25807
Change subject: soc/intel/cannonlake: Use common i2c function instead of soc
......................................................................
soc/intel/cannonlake: Use common i2c function instead of soc
In previous patch, common I2C related functionality was moved to common
folder. In this patch, moved soc dependent function to chip_config.c
file. So we can use i2c functionality from common block (i2c_v2) instead
of keeping it inside soc.
Also removed i2c.c file from inside cannonlake folder.
Change-Id: I569f407a82c09f37a31fa3e090c27acb12bf758e
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela at intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/chip_config.c
D src/soc/intel/cannonlake/i2c.c
4 files changed, 19 insertions(+), 87 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/25807/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index ebf6741..55f2ea8 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -56,7 +56,7 @@
select SOC_INTEL_COMMON_BLOCK_GRAPHICS
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_ITSS
- select SOC_INTEL_COMMON_BLOCK_I2C
+ select SOC_INTEL_COMMON_BLOCK_I2C_V2
select SOC_INTEL_COMMON_BLOCK_LPC
select SOC_INTEL_COMMON_BLOCK_LPSS
select SOC_INTEL_COMMON_BLOCK_P2SB
diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc
index 0e73c14..afebb24 100644
--- a/src/soc/intel/cannonlake/Makefile.inc
+++ b/src/soc/intel/cannonlake/Makefile.inc
@@ -15,7 +15,6 @@
bootblock-y += bootblock/report_platform.c
bootblock-y += gpio.c
bootblock-y += gspi.c
-bootblock-y += i2c.c
bootblock-y += memmap.c
bootblock-y += spi.c
bootblock-y += lpc.c
@@ -24,7 +23,6 @@
romstage-$(CONFIG_SOC_INTEL_CANNONLAKE_LPDDR4_INIT) += cnl_lpddr4_init.c
romstage-y += gpio.c
romstage-y += gspi.c
-romstage-y += i2c.c
romstage-y += lpc.c
romstage-y += memmap.c
romstage-y += pmutil.c
@@ -40,7 +38,6 @@
ramstage-y += graphics.c
ramstage-y += gspi.c
ramstage-y += gpio.c
-ramstage-y += i2c.c
ramstage-y += lpc.c
ramstage-y += memmap.c
ramstage-y += nhlt.c
@@ -65,7 +62,6 @@
postcar-$(CONFIG_UART_DEBUG) += uart.c
verstage-y += gspi.c
-verstage-y += i2c.c
verstage-y += pmutil.c
verstage-y += spi.c
verstage-$(CONFIG_UART_DEBUG) += uart.c
diff --git a/src/soc/intel/cannonlake/chip_config.c b/src/soc/intel/cannonlake/chip_config.c
index 679c062..fd29866 100644
--- a/src/soc/intel/cannonlake/chip_config.c
+++ b/src/soc/intel/cannonlake/chip_config.c
@@ -13,7 +13,9 @@
* GNU General Public License for more details.
*/
#include "chip.h"
+#include <console/console.h>
#include <device/device.h>
+#include <drivers/i2c/designware/dw_i2c.h>
#include <intelbasecode/lockdown.h>
/*
@@ -35,3 +37,19 @@
return config->chipset_lockdown;
}
+
+const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
+{
+ const struct soc_intel_cannonlake_config *config;
+ const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
+
+ if (!dev || !dev->chip_info) {
+ printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
+ __func__);
+ return NULL;
+ }
+
+ config = dev->chip_info;
+
+ return &config->i2c[bus];
+}
diff --git a/src/soc/intel/cannonlake/i2c.c b/src/soc/intel/cannonlake/i2c.c
deleted file mode 100644
index ef30345..0000000
--- a/src/soc/intel/cannonlake/i2c.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- * Copyright (C) 2017 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci_def.h>
-#include <drivers/i2c/designware/dw_i2c.h>
-#include <soc/iomap.h>
-#include <soc/pci_devs.h>
-#include "chip.h"
-
-const struct dw_i2c_bus_config *dw_i2c_get_soc_cfg(unsigned int bus)
-{
- const struct soc_intel_cannonlake_config *config;
- const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
-
- if (!dev || !dev->chip_info) {
- printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",
- __func__);
- return NULL;
- }
-
- config = dev->chip_info;
-
- return &config->i2c[bus];
-}
-
-uintptr_t dw_i2c_get_soc_early_base(unsigned int bus)
-{
- return EARLY_I2C_BASE(bus);
-}
-
-int dw_i2c_soc_devfn_to_bus(unsigned int devfn)
-{
- switch (devfn) {
- case PCH_DEVFN_I2C0:
- return 0;
- case PCH_DEVFN_I2C1:
- return 1;
- case PCH_DEVFN_I2C2:
- return 2;
- case PCH_DEVFN_I2C3:
- return 3;
- case PCH_DEVFN_I2C4:
- return 4;
- case PCH_DEVFN_I2C5:
- return 5;
- }
- return -1;
-}
-
-int dw_i2c_soc_bus_to_devfn(unsigned int bus)
-{
- switch (bus) {
- case 0:
- return PCH_DEVFN_I2C0;
- case 1:
- return PCH_DEVFN_I2C1;
- case 2:
- return PCH_DEVFN_I2C2;
- case 3:
- return PCH_DEVFN_I2C3;
- case 4:
- return PCH_DEVFN_I2C4;
- case 5:
- return PCH_DEVFN_I2C5;
- }
- return -1;
-}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I569f407a82c09f37a31fa3e090c27acb12bf758e
Gerrit-Change-Number: 25807
Gerrit-PatchSet: 1
Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela at intel.com>
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