[coreboot-gerrit] Change in coreboot[master]: mb/google/bip: Configure pins to reflect delta w.r.t yorp

[Shamile Khan (Code Review)]

Shamile Khan has uploaded this change for review. ( https://review.coreboot.org/25804


Change subject: mb/google/bip: Configure pins to reflect delta w.r.t yorp
......................................................................

mb/google/bip: Configure pins to reflect delta w.r.t yorp

Changes in pin usage between yorp and bip
- LTE_OFF_ODL pin moved from GPIO_66 to GPIO_161
- I2S0 interface is not used in bip. It was used in
yorp for DMIC Wake on Voice through Nuvoton EC.

BUG=b:77869623
BRANCH=none
TEST=Build coreboot for bip.

Change-Id: I8907bd63a43c4bc51ca991c3ec7c1cae9e39e2d1
Signed-off-by: Shamile Khan <shamile.khan at intel.com>
---
M src/mainboard/google/octopus/variants/bip/gpio.c
1 file changed, 8 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/25804/1

diff --git a/src/mainboard/google/octopus/variants/bip/gpio.c b/src/mainboard/google/octopus/variants/bip/gpio.c
index fe7a2e2..f510023 100644
--- a/src/mainboard/google/octopus/variants/bip/gpio.c
+++ b/src/mainboard/google/octopus/variants/bip/gpio.c
@@ -90,7 +90,7 @@
 	PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
-	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B */
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* UART2-RTS_B -- LTE_OFF_ODL*/
 	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, Tx0RxDCRx0, DISPUPD), /* UART2-CTS_B */
 	PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */
 	PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */
@@ -206,15 +206,15 @@
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_144, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_VDDN */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_145, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTEN */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, NONE, DEEP, NF5, HIZCRx0, DISPUPD),/* PANEL1_BKLTCTL */
-	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_154, 1, DEEP, UP_20K, HIZCRx1, DISPUPD),/* LPC_CLKRUNB -- LTE_OFF_ODL */
+	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_154, 1, DEEP, UP_20K, HIZCRx1, DISPUPD),/* LPC_CLKRUNB */
 
 	/* AUDIO COMMUNITY GPIOS*/
-	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_156, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* AVS_I2S0_MCLK */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_BCLK */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_WS_SYNC */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_SDI */
-	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_160, NONE, DEEP, NF1, HIZCRx0, ENPD), /* AVS_I2S0_SDO */
-	PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 0, DEEP, NONE, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */
+	PAD_CFG_GPIO_HI_Z(GPIO_156, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_MCLK -- unused */
+	PAD_CFG_GPIO_HI_Z(GPIO_157, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_BCLK -- unused */
+	PAD_CFG_GPIO_HI_Z(GPIO_158, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_WS_SYNC -- unused */
+	PAD_CFG_GPIO_HI_Z(GPIO_159, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_SDI -- unused */
+	PAD_CFG_GPIO_HI_Z(GPIO_160, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S0_SDO -- unused */
+	PAD_CFG_GPIO_HI_Z(GPIO_161, NONE, DEEP, HIZCRx0, DISPUPD),/* AVS_I2S1_MCLK -- unused */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */
 	PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */
 	PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I8907bd63a43c4bc51ca991c3ec7c1cae9e39e2d1
Gerrit-Change-Number: 25804
Gerrit-PatchSet: 1
Gerrit-Owner: Shamile Khan <shamile.khan at intel.com>
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