[coreboot-gerrit] Change in coreboot[master]: [WIP/TODO] arch/riscv: Configure delegation only in ramstage

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25791


Change subject: [WIP/TODO] arch/riscv: Configure delegation only in ramstage
......................................................................

[WIP/TODO] arch/riscv: Configure delegation only in ramstage

On the FU540 the bootblock runs on a core without lesser privilege
modes, so the medeleg/mideleg CSRs are not implemented on that core.

Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/arch/riscv/virtual_memory.c
1 file changed, 3 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/25791/1

diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 3bee868..7830519 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -54,9 +54,10 @@
 
 	// Delegate supervisor timer and other interrupts
 	// to supervisor mode.
-	set_csr(mideleg,  MIP_STIP | MIP_SSIP);
+	//set_csr(mideleg,  MIP_STIP | MIP_SSIP);
 
-	set_csr(medeleg, delegate);
+	//set_csr(medeleg, delegate);
+	(void)delegate;
 
 	// Enable all user/supervisor-mode counters using
 	// v1.10 register addresses.

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idad97e42bac2ff438dd233a5d125f93594505d63
Gerrit-Change-Number: 25791
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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