[coreboot-gerrit] Change in coreboot[master]: RISC-V boards: Remove PAGETABLES sections from memlayout.ld

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25701


Change subject: RISC-V boards: Remove PAGETABLES sections from memlayout.ld
......................................................................

RISC-V boards: Remove PAGETABLES sections from memlayout.ld

RISC-V doesn't setup page tables anymore, since commit b26759d703
("arch/riscv: Don't set up virtual memory").

Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/arch/riscv/include/arch/memlayout.h
M src/mainboard/emulation/qemu-riscv/memlayout.ld
M src/mainboard/emulation/spike-riscv/memlayout.ld
M src/mainboard/lowrisc/nexys4ddr/memlayout.ld
4 files changed, 2 insertions(+), 4 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/25701/1

diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h
index 5d01141..9097cf5 100644
--- a/src/arch/riscv/include/arch/memlayout.h
+++ b/src/arch/riscv/include/arch/memlayout.h
@@ -19,7 +19,6 @@
 #define __ARCH_MEMLAYOUT_H
 
 #define STACK(addr, size) REGION(stack, addr, size, 4096)
-#define PAGETABLES(addr, size) REGION(pagetables, addr, size, 4096)
 
 /* TODO: Need to add DMA_COHERENT region like on ARM? */
 
diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld
index 8cc6d41..615d1f2 100644
--- a/src/mainboard/emulation/qemu-riscv/memlayout.ld
+++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld
@@ -24,6 +24,5 @@
 	ROMSTAGE(0x20000, 128K)
 	STACK(0x40000, 0x3ff00)
 	PRERAM_CBMEM_CONSOLE(0x80000, 8K)
-	PAGETABLES(0x80000+8K, 60K)
 	RAMSTAGE(0x100000, 16M)
 }
diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld
index 8596723..bae414f 100644
--- a/src/mainboard/emulation/spike-riscv/memlayout.ld
+++ b/src/mainboard/emulation/spike-riscv/memlayout.ld
@@ -24,7 +24,7 @@
 	DRAM_START(START)
 	BOOTBLOCK(START, 64K)
 	STACK(START + 8M, 4K)
-	PAGETABLES(START + 8M + 4K, 60K)
+	/* hole at (START + 8M + 4K, 60K) */
 	ROMSTAGE(START + 8M + 64K, 128K)
 	PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
 	RAMSTAGE(START + 8M + 200K, 256K)
diff --git a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld
index 0348c47..86f3667 100644
--- a/src/mainboard/lowrisc/nexys4ddr/memlayout.ld
+++ b/src/mainboard/lowrisc/nexys4ddr/memlayout.ld
@@ -26,6 +26,6 @@
 	STACK(START + 8M, 64K)
 	ROMSTAGE(START + 8M + 64K, 128K)
 	PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K)
-	PAGETABLES(START + 8M + 200K, 56K)
+	/* hole at (START + 8M + 200K, 56K) */
 	RAMSTAGE(START + 8M + 256K, 256K)
 }

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0
Gerrit-Change-Number: 25701
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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