[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Adjust LPC Generic IO setup

[Lijian Zhao (Code Review)]

Lijian Zhao has uploaded this change for review. ( https://review.coreboot.org/25667


Change subject: soc/intel/common: Adjust LPC Generic IO setup
......................................................................

soc/intel/common: Adjust LPC Generic IO setup

Check same IO ranges get programmed first, if so just skip it to avoid double
programming.

BUG=b:77944335
TEST=Boot up with mewoth board, and check serial log, there's no error
message about "LPC: Cannot Open IO Window: ".

Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c
Signed-off-by: Lijian Zhao <lijian.zhao at intel.com>
---
M src/soc/intel/common/block/lpc/lpc_lib.c
1 file changed, 18 insertions(+), 11 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/25667/1

diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index aeac441..58b588e 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -65,7 +65,7 @@
 
 void lpc_open_pmio_window(uint16_t base, uint16_t size)
 {
-	int lgir_reg_num;
+	int i, lgir_reg_num;
 	uint32_t lgir_reg_offset, lgir, window_size, alignment;
 	resource_t bridged_size, bridge_base;
 
@@ -76,16 +76,6 @@
 	bridge_base = base;
 
 	while (bridged_size < size) {
-		lgir_reg_num = find_unused_pmio_window();
-		if (lgir_reg_num < 0) {
-			printk(BIOS_ERR,
-				"LPC: Cannot open IO window: %llx size %llx\n",
-				bridge_base, size - bridged_size);
-			printk(BIOS_ERR, "No more IO windows\n");
-			return;
-		}
-		lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
-
 		/* Each IO range register can only open a 256-byte window. */
 		window_size = MIN(size, LPC_LGIR_MAX_WINDOW_SIZE);
 
@@ -97,6 +87,23 @@
 		lgir = (bridge_base & LPC_LGIR_ADDR_MASK) | LPC_LGIR_EN;
 		lgir |= ((window_size - 1) << 16) & LPC_LGIR_AMASK_MASK;
 
+		/* Skip programming if same range already programmed. */
+		for (i = 0; i < LPC_NUM_GENERIC_IO_RANGES; i++) {
+			if (lgir == pci_read_config32(PCH_DEV_LPC,
+						LPC_GENERIC_IO_RANGE(i)))
+				return;
+		}
+
+		lgir_reg_num = find_unused_pmio_window();
+		if (lgir_reg_num < 0) {
+			printk(BIOS_ERR,
+				"LPC: Cannot open IO window: %llx size %llx\n",
+				bridge_base, size - bridged_size);
+			printk(BIOS_ERR, "No more IO windows\n");
+			return;
+		}
+		lgir_reg_offset = LPC_GENERIC_IO_RANGE(lgir_reg_num);
+
 		pci_write_config32(PCH_DEV_LPC, lgir_reg_offset, lgir);
 
 		printk(BIOS_DEBUG,

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c
Gerrit-Change-Number: 25667
Gerrit-PatchSet: 1
Gerrit-Owner: Lijian Zhao <lijian.zhao at intel.com>
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