[coreboot-gerrit] Change in coreboot[master]: intel/fsp_broadwell_de: Remove buggy code for SMBus clock gating

[Werner Zeh (Code Review)]

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/25652


Change subject: intel/fsp_broadwell_de: Remove buggy code for SMBus clock gating
......................................................................

intel/fsp_broadwell_de: Remove buggy code for SMBus clock gating

The pch_smbus_init() function contains code to enable clock gating for
the SMBus controller. Unfortunately this code is buggy and leads to a
hanging system hang which occurs as follows:
The clock gate register is mapped into RCBA space. After reading the
RCBA address from the LPC device config space no mask is applied to the
value (only bits 31..14 are valid while bit 0 is the enable bit). For
this reason the final address is off by one. The old microcodes at least
allowed this unaligned access to the RCBA space. With the latest
microcode this access leads to CPU hang.

Once this is fixed the next issue occurs: After setting the clock
gating bit for SMBus (bit 5) the SMBus controller disappears from the
PCI bus completely and hence no usage of it is possible anymore.

To fix this issue the clock gating code is completely removed as it was
intentionally meant to enable clock gating on the SMB_CLK line and not
the clock gating on the PCIe interface of the SMBus controller.

This issue is known already and was discussed on the mailinglist:
https://mail.coreboot.org/pipermail/coreboot/2018-January/085908.html

Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33
Signed-off-by: Werner Zeh <werner.zeh at siemens.com>
---
M src/soc/intel/fsp_broadwell_de/smbus.c
1 file changed, 0 insertions(+), 8 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/25652/1

diff --git a/src/soc/intel/fsp_broadwell_de/smbus.c b/src/soc/intel/fsp_broadwell_de/smbus.c
index 480e497..039f841 100644
--- a/src/soc/intel/fsp_broadwell_de/smbus.c
+++ b/src/soc/intel/fsp_broadwell_de/smbus.c
@@ -29,14 +29,6 @@
 static void pch_smbus_init(device_t dev)
 {
 	struct resource *res;
-	uint32_t reg32;
-	device_t lpc_dev = dev_find_slot(0, LPC_DEV_FUNC);
-	void *rcba = (void *)pci_read_config32(lpc_dev, 0xf0);
-
-	/* Enable clock gating */
-	reg32 =read32(rcba + 0x341c);
-	reg32 |= (1 << 5);
-	write32(rcba + 0x341c, reg32);
 
 	/* Set Receive Slave Address */
 	res = find_resource(dev, PCI_BASE_ADDRESS_4);

-- 
To view, visit https://review.coreboot.org/25652
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33
Gerrit-Change-Number: 25652
Gerrit-PatchSet: 1
Gerrit-Owner: Werner Zeh <werner.zeh at siemens.com>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.coreboot.org/pipermail/coreboot-gerrit/attachments/20180413/2370300d/attachment.html>