[coreboot-gerrit] Change in coreboot[master]: arch/riscv: Store mprv bit in size_t

[Jonathan Neuschäfer (Code Review)]

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/25625


Change subject: arch/riscv: Store mprv bit in size_t
......................................................................

arch/riscv: Store mprv bit in size_t

CSRs are XLEN bits wide (i.e. the same width as general purpose
registers), so size_t seems a little more correct than int.

This change doesn't affect functionality because MSTATUS_MPRV already
fits in 31 bits.

Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
---
M src/arch/riscv/include/vm.h
1 file changed, 2 insertions(+), 2 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/25625/1

diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h
index fd0a2c9..a30d6bb 100644
--- a/src/arch/riscv/include/vm.h
+++ b/src/arch/riscv/include/vm.h
@@ -42,7 +42,7 @@
 	static inline type name(type *p);				\
 	static inline type name(type *p)				\
 	{								\
-		int mprv = MSTATUS_MPRV;				\
+		size_t mprv = MSTATUS_MPRV;				\
 		type value;						\
 		asm (							\
 			"csrs		mstatus, %1\n"			\
@@ -57,7 +57,7 @@
 	static inline void name(type *p, type value);			\
 	static inline void name(type *p, type value)			\
 	{								\
-		int mprv = MSTATUS_MPRV;				\
+		size_t mprv = MSTATUS_MPRV;				\
 		asm (							\
 			"csrs		mstatus, %0\n"			\
 			STRINGIFY(insn) " %1, 0(%2)\n"			\

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5
Gerrit-Change-Number: 25625
Gerrit-PatchSet: 1
Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer at gmx.net>
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