[coreboot-gerrit] Change in coreboot[master]: nb/intel/pineview: Put stage cache in TSEG
Arthur Heymans (Code Review)
gerrit at coreboot.org
Tue Apr 10 16:18:38 CEST 2018
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25605
Change subject: nb/intel/pineview: Put stage cache in TSEG
......................................................................
nb/intel/pineview: Put stage cache in TSEG
TSEG is not accessible in ring 0 after it is locked in ramstage, in
contrast with cbmem which remains accessible. Assuming SMM does not
touch the cache this is a good region to cache stages.
Untested.
Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/pineview/Makefile.inc
A src/northbridge/intel/pineview/stage_cache.c
3 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/25605/1
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index 9e5a1c1..5b5b20d 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -31,6 +31,7 @@
select INTEL_GMA_ACPI
select SMM_TSEG
select PARALLEL_MP
+ select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
config BOOTBLOCK_NORTHBRIDGE_INIT
string
@@ -40,4 +41,13 @@
string
default "8086,a001"
+config SMM_RESERVED_SIZE
+ hex
+ default 0x100000
+
+# Intel Enhanced Debug region must be 4MB
+config IED_REGION_SIZE
+ hex
+ default 0x400000
+
endif
diff --git a/src/northbridge/intel/pineview/Makefile.inc b/src/northbridge/intel/pineview/Makefile.inc
index a4c08c8..8e8b393 100644
--- a/src/northbridge/intel/pineview/Makefile.inc
+++ b/src/northbridge/intel/pineview/Makefile.inc
@@ -25,4 +25,7 @@
romstage-y += raminit.c
romstage-y += early_init.c
+romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
+
endif
diff --git a/src/northbridge/intel/pineview/stage_cache.c b/src/northbridge/intel/pineview/stage_cache.c
new file mode 100644
index 0000000..bbe4fcd
--- /dev/null
+++ b/src/northbridge/intel/pineview/stage_cache.c
@@ -0,0 +1,38 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <cbmem.h>
+#include <device/pci.h>
+#include <stage_cache.h>
+#include "pineview.h"
+
+void stage_cache_external_region(void **base, size_t *size)
+{
+ /*
+ * The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET.
+ * The top of RAM is defined to be the TSEG base address.
+ */
+ *size = CONFIG_SMM_RESERVED_SIZE;
+#ifdef __SIMPLE_DEVICE__
+ const u8 esmramc = pci_read_config8(PCI_DEV(0, 0x00, 0), ESMRAMC);
+#else
+ const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)),
+ ESMRAMC);
+#endif
+ const u32 tseg_size = decode_tseg_size(esmramc);
+ *base = (void *)((uintptr_t)cbmem_top() + tseg_size
+ - CONFIG_SMM_RESERVED_SIZE - CONFIG_IED_REGION_SIZE);
+}
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I3d163e8ff328ba01425b524a673f34a96fb93ea7
Gerrit-Change-Number: 25605
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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