[coreboot-gerrit] Change in coreboot[master]: nb/intel/pineview: Use common code for SMM in TSEG

[Arthur Heymans (Code Review)]

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/25598


Change subject: nb/intel/pineview: Use common code for SMM in TSEG
......................................................................

nb/intel/pineview: Use common code for SMM in TSEG

Untested.

Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52
Signed-off-by: Arthur Heymans <arthur at aheymans.xyz>
---
M src/northbridge/intel/pineview/Kconfig
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/pineview/pineview.h
M src/northbridge/intel/pineview/ram_calc.c
4 files changed, 59 insertions(+), 0 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/25598/1

diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index e8ef9d9..047aa8b 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -29,6 +29,7 @@
 	select INTEL_EDID if MAINBOARD_DO_NATIVE_VGA_INIT
 	select RELOCATABLE_RAMSTAGE
 	select INTEL_GMA_ACPI
+	select SMM_TSEG
 
 config BOOTBLOCK_NORTHBRIDGE_INIT
 	string
diff --git a/src/northbridge/intel/pineview/northbridge.c b/src/northbridge/intel/pineview/northbridge.c
index ea55974..cf6c5ce 100644
--- a/src/northbridge/intel/pineview/northbridge.c
+++ b/src/northbridge/intel/pineview/northbridge.c
@@ -26,6 +26,7 @@
 #include <boot/tables.h>
 #include <arch/acpi.h>
 #include <northbridge/intel/pineview/pineview.h>
+#include <cpu/intel/smm/gen1/smi.h>
 
 /* Reserve everything between A segment and 1MB:
  *
@@ -127,6 +128,43 @@
 	add_fixed_resources(dev, index);
 }
 
+u32 northbridge_get_tseg_size(void)
+{
+	const u8 esmramc = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 0)),
+					ESMRAMC);
+	return decode_tseg_size(esmramc);
+}
+
+u32 northbridge_get_tseg_base(void)
+{
+	return pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG);
+}
+
+void northbridge_write_smram(u8 smram)
+{
+	pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, smram);
+}
+
+/*
+ * Really doesn't belong here but will go away with parallel mp init,
+ * so let it be here for a while...
+ */
+int cpu_get_apic_id_map(int *apic_id_map)
+{
+	unsigned int i;
+
+	/* Logical processors (threads) per core */
+	const struct cpuid_result cpuid1 = cpuid(1);
+	/* Read number of cores. */
+	const char cores = (cpuid1.ebx >> 16) & 0xf;
+
+	/* TODO in parallel MP cpuid(1).ebx */
+	for (i = 0; i < cores; i++)
+		apic_id_map[i] = i;
+
+	return cores;
+}
+
 static void mch_domain_set_resources(device_t dev)
 {
 	struct resource *res;
diff --git a/src/northbridge/intel/pineview/pineview.h b/src/northbridge/intel/pineview/pineview.h
index 9873d4d..e064d94 100644
--- a/src/northbridge/intel/pineview/pineview.h
+++ b/src/northbridge/intel/pineview/pineview.h
@@ -233,6 +233,7 @@
 void pineview_early_initialization(void);
 u32 decode_igd_memory_size(const u32 gms);
 u32 decode_igd_gtt_size(const u32 gsm);
+u32 decode_tseg_size(const u32 esmramc);
 u8 decode_pciebar(u32 *const base, u32 *const len);
 
 /* provided by mainboard code */
diff --git a/src/northbridge/intel/pineview/ram_calc.c b/src/northbridge/intel/pineview/ram_calc.c
index 63f3942..1d712f2 100644
--- a/src/northbridge/intel/pineview/ram_calc.c
+++ b/src/northbridge/intel/pineview/ram_calc.c
@@ -94,6 +94,25 @@
 	return (u32)(gsmsize[gsm] << 10);
 }
 
+/** Decodes used TSEG size to bytes. */
+u32 decode_tseg_size(const u32 esmramc)
+{
+	if (!(esmramc & 1))
+		return 0;
+
+	switch ((esmramc >> 1) & 3) {
+	case 0:
+		return 1 << 20;
+	case 1:
+		return 2 << 20;
+	case 2:
+		return 8 << 20;
+	case 3:
+	default:
+		die("Bad TSEG setting.\n");
+	}
+}
+
 /* Depending of UMA and TSEG configuration, TSEG might start at any
  * 1 MiB aligment. As this may cause very greedy MTRR setup, push
  * CBMEM top downwards to 4 MiB boundary.

-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: I5f947cfae730b67bc76a581bc90cb10e5a2a4a52
Gerrit-Change-Number: 25598
Gerrit-PatchSet: 1
Gerrit-Owner: Arthur Heymans <arthur at aheymans.xyz>
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